Intel Pentium II, Developer'S Manual

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DATA INTEGRITY
E
4-2
8/26/97 12:55 PM CH04.DOC
INTEL CONFIDENTIAL
(until publication date)
•
Recoverable Error (RE): The error can be corrected by a retry or by using ECC
information. The error is logged in the MCA hardware.
•
Unrecoverable Error (UE): The error cannot be corrected, but it only affects one agent.
The memory interface logic and bus pipeline are intact, and can be used to report the
error via an exception handler.
•
Fatal Error (FE): The error cannot be corrected and may affect more than one agent.
The memory interface logic and bus pipeline integrity may have been violated, and
cannot be reliably used to report the error via an exception handler. A bus pipeline reset
is required of all bus agents before operation can continue. An exception handler may
then proceed.
4.2. PENTIUM
®
II PROCESSOR SYSTEM BUS DATA INTEGRITY
ARCHITECTURE
The Pentium II processor system bus’ major address and data paths are protected by ten
check bits, providing parity or ECC. Eight ECC bits protect the data bus. Single-bit data ECC
errors are automatically corrected. A two-bit parity code protects the address bus. Any
address parity error on the address bus when the request is issued can be optionally retried to
attempt a correction.
Two control signal groups are explicitly protected by individual parity bits: RP# and RSP#.
Errors on most remaining bus signals can be detected indirectly due to a well-defined bus
protocol specification that enables detection of protocol violation errors. Errors on a few bus
signals cannot be detected without the use of FRC mode.
An agent is not required to support all data integrity features, as each feature is individually
enabled through the power-on configuration register. See Chapter 5, Configuration.
4.2.1. Bus Signals Protected Directly
Most Pentium II processor system bus signals are protected by parity or ECC. Table 4-1
shows which signals protect which signals.
Table 4-1. Direct Bus Signal Protection
Signal Protects
RP# ADS#,REQ[4:0]#
AP[0]# A[23:3]#
AP[1]# A[35:24]#
RSP# RS[2:0]#
DEP[7:0]# D[63:0]#