Intel Pentium II, Developer'S Manual, Page: 43 / 226

E
SYSTEM BUS OVERVIEW
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8/26/97 12:47 PM CH03.DOC
INTEL CONFIDENTIAL
(until publication date)
checker, and the pair operates as a single processor. If the checker agent detects a mismatch
between its internally sampled outputs and the master processor’s outputs, the checker asserts
FRCERR. FRCERR observation can be enabled at the master processor with software. The
master enters machine check on an FRCERR provided that Machine Check Execution is
enabled.
The FRCERR signal is also toggled during an FRC checker agent’s reset action. FRCERR is
asserted one clock after RESET# transitions from its active to inactive state. If the checker
processor executes its built-in self test (BIST), then FRCERR is asserted throughout that test.
After BIST completes, the checker processor desserts FRCERR only if BIST succeeded but
continues to assert FRCERR if BIST failed. This feature allows the failure to be externally
observed. If the checker processor does not execute its BIST, then it keeps FRCERR asserted
for less than 20 clocks and then deasserts it.
3.2.8. Compatibility Signals
The compatibility signals group (see Table 3-8) contains signals defined for compatibility
within the Intel Architecture processor family.
Table 3-8. PC Compatibility Signals
Type Signal Names
Floating-Point Error FERR#
Ignore Numeric Error IGNNE#
Address 20 Mask A20M#
System Management Interrupt SMI#
A P6 family agent asserts FERR# when it detects an unmasked floating-point error. FERR# is
included for compatibility with systems using DOS-type floating-point error reporting.
If the IGNNE# input signal is asserted, the processor ignores a numeric error and continues to
execute non-control floating-point instructions. If the IGNNE# input signal is deasserted, the
processor freezes on a non-control floating-point instruction if a previous instruction caused
an error.
If the A20M# input signal is asserted, the processor masks physical address bit 20 (A20#)
before looking up a line in any internal cache and before driving a memory read/write
transaction on the bus. Asserting A20M# emulates the 8086 processor’s address wraparound
at the one Mbyte boundary. A20M# must only be asserted when the processor is in real
mode. A20M# is not used to mask external snoop addresses.
The IGNNE# and A20M# signals are valid at all times. These signals are normally not
guaranteed recognition at specific boundaries.