Intel Pentium II, Developer'S Manual

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SYSTEM BUS OVERVIEW
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3-6
8/26/97 12:47 PM CH03.DOC
INTEL CONFIDENTIAL
(until publication date)
On observing a transaction, HIT# and HITM# are used to indicate that the line is valid or
invalid in the snooping agent, whether the line is in the modified (dirty) state in the caching
agent, or whether the transaction needs to be extended. The HIT# and HITM# signals are
used to maintain cache coherency at the system level.
If the memory agent observes HITM# active, it relinquishes responsibility for the data return
and becomes a target for the implicit cache line writeback. The memory agent must merge
the cache line being written back with any write data and update memory. The memory agent
must also provide the implicit writeback response for the transaction.
If HIT# and HITM# are sampled asserted together, it means that a caching agent is not ready
to indicate snoop status, and it needs to extend the transaction.
DEFER# is deasserted to indicate that the transaction can be guaranteed in-order completion.
An agent asserting DEFER# ensures proper removal of the transaction from the In-order
Queue by generating the appropriate response.
3.2.5. Response Signals
The response signal group (see Table 3-5) provides response information to the requesting
agent.
Table 3-5. Response Signals
Type Signal Names
Response Status RS[2:0]#
Response Parity RSP#
Target Ready (for writes) TRDY#
Requests initiated in the Request Phase enter the In-order Queue, which is maintained by
every agent. The response agent is the agent responsible for completing the transaction at the
top of the In-order Queue. The response agent is the agent addressed by the transaction.
For write transactions, TRDY# is asserted by the response agent to indicate that it is ready to
accept write or writeback data. For write transactions with an implicit writeback, TRDY# is
asserted twice, first for the write data transfer and then again for the implicit writeback data
transfer.
The RSP# signal provides parity for RS[2:0]#. A parity signal on the System bus is correct if
there are an even number of low signals in the set consisting of the covered signals plus the
parity signal. Parity is computed using voltage levels, regardless of whether the covered
signals are active high or active low.