Intel Pentium II, Developer'S Manual

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E
CONFIGURATION
5-7
8/26/97 1:02 PM CH05.DOC
INTEL CONFIDENTIAL
(until publication date)
and IGNNE# on the inactive-to-active transition of RESET# to determine the core-frequency
to bus-frequency relationship and immediately begins the internal PLL lock mode. On the
active-to-inactive transition of RESET#, the processor internally latches the inputs to allow
the pins to be used for normal functionality. Effectively, these pins must meet a large setup
time (1 ms) to the active-to-inactive transition of RESET#.
Table 7-1 describes the relationship between bus frequency and core frequency.
5.3. SOFTWARE-PROGRAMMABLE OPTIONS
All bus agents are required to maintain some software read/writeable bits in the power-on
configuration register for software-configured options. This register inside P6 family
processors is defined in Table 5-4.
Table 5-4. Pentium ® II Processor Family Power-On Configuration Register
Feature
Processor
Active Signals
Processor
Register
Bits Read/Write Default
Output tristate enabled FLUSH# D8=1 Read N/A
Execute BIST INIT# D9=1 Read N/A
Data error checking enabled N/A D1=1 Read/Write Disabled
Response error checking enabled
FRCERR observation enabled N/A D2=1 Read/Write Disabled
AERR# driver enabled N/A D3=1 Read/Write Disabled
AERR# observation enabled A8# D10=1 Read N/A
BERR# driver enabled for initiator bus
requests N/A D4=1 Read/Write Disabled
BERR# driver enabled for target bus
requests N/A Reserved Read/Write Disabled
BERR# driver enabled for initiator
internal errors N/A D6=1 Read/Write Disabled
BERR# observation enabled A9# Reserved Read N/A
BINIT# driver enabled N/A D7=1 Read/Write Disabled
BINIT# observation enabled A10# D12=1 Read N/A
In-order queue depth of 1 A7# D13=1 Read N/A
1 Mbyte power-on reset vector A6# D14=1 Read N/A
FRC Mode enabled A5# D15=1 Read N/A
APIC cluster ID A12#, A11# D17, D16
see Table 5-5 Read N/A
Reserved A14#, A13# D19, D18 — —
Symmetric arbitration ID BR0#, BR1#,
BR2#, BR3#,
A5# D21,D20
see Table 5-6 Read N/A