Intel Extensible Firmware Interface, Specification

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32/64-bit UNDI Specification
Version 1.02 12/12/00 381
Table G-4. !PXE Structure Field Definitions (continued)
Identifier Value Description
Status Varies UNDI operation, command and interrupt status flags.
This is a read-only port. Undefined status bits must be set to zero. Reading
this port does NOT clear the status.
Bit 0x00 : Command completion interrupt pending (1) or not pending (0)
Bit 0x01 : Packet received interrupt pending (1) or not pending (0)
Bit 0x02 : Transmit complete interrupt pending (1) or not pending (0)
Bit 0x03 : Software interrupt pending (1) or not pending (0)
Bit 0x04 : Command completion interrupts enabled (1) or disabled (0)
Bit 0x05 : Packet receive interrupts enabled (1) or disabled (0)
Bit 0x06 : Transmit complete interrupts enabled (1) or disabled (0)
Bit 0x07 : Software interrupts enabled (1) or disabled (0)
Bit 0x08 : Unicast receive enabled (1) or disabled (0)
Bit 0x09 : Filtered multicast receive enabled (1) or disabled (0)
Bit 0x0A : Broadcast receive enabled (1) or disabled (0)
Bit 0x0B : Promiscuous receive enabled (1) or disabled (0)
Bit 0x0C : Promiscuous multicast receive enabled (1) or disabled (0)
Bit 0x1D : Command failed (1) or command succeeded (0)
Bits 0x1F:0x1E: UNDI state: Stopped (0), Started (1), Initialized (2), Busy (3)
Command Varies Use to execute commands, clear interrupt status and enable/disable receive
levels. This is a read/write port. Read reflects the last write.
Bit 0x00: Clear command completion interrupt (1) or NOP (0)
Bit 0x01: Clear packet received interrupt (1) or NOP (0)
Bit 0x02: Clear transmit complete interrupt (1) or NOP (0)
Bit 0x03: Clear software interrupt (1) or NOP (0)
Bit 0x04: Command completion interrupt enable (1) or disable (0)
Bit 0x05: Packet receive interrupt enable (1) or disable (0)
Bit 0x06: Transmit complete interrupt enable (1) or disable (0)
Bit 0x07: Software interrupt enable (1) or disable (0). Setting this bit to (1)
also generates a software interrupt.
Bit 0x08: Unicast receive enable (1) or disable (0)
Bit 0x09: Filtered multicast receive enable (1) or disable (0)
Bit 0x0A: Broadcast receive enable (1) or disable (0)
Bit 0x0B: Promiscuous receive enable (1) or disable (0)
Bit 0x0C: Promiscuous multicast receive enable (1) or disable (0)
Bit 0x1F: Operation type: Clear interrupt and/or filter (0), Issue command (1)
CDBaddr Varies Write the physical address of a CDB to this port. (Done with one 64-bit or two
32-bit writes, depending on CPU architecture.) When done, use one 32-bit
write to the command port to send this address into the command queue.
Unused upper address bits must be set to zero.
continued