Functional Architecture
Intel
®
Server Board S5500BC TPS
Intel order number: E42249-003
Revision 1.0
34
Manageability Engine Power Management Support for new wake events from the IOH
Management Engine.
The Intel
®
Server Board S5500BC server is fully compliant with the Advanced Configuration and
Power Interface (ACPI) specifications, Revision 2.0.
3.4.9
System Management Interface
Intel
®
ICH10R on the Intel
®
Server board S5500BC functions as a SMBus Host Controller that
allows the processor to communicate with SMBus slaves. This interface is compatible with most
I
2
C devices. Intel
®
ICH10R also supports slave functionality.
3.4.10
Real Time Clock (RTC)
Intel
®
ICH10R contains a Motorola MS146818A* functionally compatible Real Time Clock (RTC)
with two 128-byte banks of battery-backed RAM. The RTC performs two key functions on the
Intel
®
Server Board S5500BC:
Keeps track of the time of day
Stores System configuration data even when the system is powered down.
The RTC operates on a 32.768 KHz crystal and a 3-V lithium battery.
3.4.11 Manageability
Intel
®
ICH10R integrates several functions designed to manage the system and lower the total
cost of ownership (TCO) of the system. These system management functions are designed to
report errors, diagnose the system, and recover from system lockups without the aid of an
external microcontroller.
The management engine includes:
TCO Timer: Detects system locks
Process Present Indicator: Determines the processor fetches the first instruction after
reset.
ECC Error Reporting: Reports ECC errors from the host controller.
Function Disable: Prevents a disabled function from generating interrupts and power
management events.
Intruder Detect Input: Determines system cases.
3.4.12 Unsupported
Intel
®
ICH10R Interfaces
The Intel
®
Server Board S5500BC does not support the following interfaces on the Intel
®
ICH10R:
