Intel
®
Server Board S5500BC TPS
Functional Architecture
Revision 1.0
Intel order number: E42249-003
25
Table 6. DIMM Population configurations
S# Speed
DIMM1
DIMM0
1 DDR3-800/1066/1333
Empty
Single
rank
2 DDR3-800/1066/1333
Empty
Dual
rank
3
DDR3-800/1066/1333
Single rank
Single rank
4
DDR3-800/1066/1333
Single rank
Dual rank
5
DDR3-800/1066/1333
Dual rank
Single rank
6
DDR3-800/1066/1333
Dual rank
Dual rank
3.2.3
Memory Upgrade Guidelines
Upgrading the system memory requires careful positioning of the DDR3 DIMMs based on the
following factors:
The current RAS mode of operation.
The existing DDR3 DIMM population.
The DDR3 DIMM characteristics.
The optimization techniques used by the Intel
®
Xeon
®
processor 5500 series to
maximize memory bandwidth.
In Independent Channel Mode all DDR3 channels operate independently. Slot-to-slot DIMM
matching is not required across channels. For example, DIMM_A1 and DIMM_B1 do not have
to match in terms of size, organization, and timing. DIMMs in a channel can be a different size
and organization, but they will operate at the maximum common frequency. You can use
Independent Channel Mode to support a single DIMM configuration in channel A and Single
Channel Mode.
You should observe the following general rules when selecting and configuring memory to
obtain the best performance from the system.
The Independent Channel Mode is the default maximum performance mode preferred
for Intel
®
Xeon
®
processor 5500 series based platforms.
Socket1 usually has precedence over socket 2 in determining the possible RAS modes.
The sockets are autonomous and capable of being independently initialized. However,
the minimal upgrade for socket 2 is DIMM_D1 in Independent Channel Mode.
Minimal upgrade for Channel Mirror mode is {D1, E1}. If this mode fails, then the
Independent channel mode is used across the sockets.
If an installed DDR3 DIMM has faulty or incompatible SPD data, it is ignored during the
memory initialization and therefore essentially disabled by the BIOS. If the DDR3 DIMM
has no or missing SPD information, the BIOS ignores the DIMM and the slot is marked
as empty.
The DDR3 DIMM populated in slot DIMM_B1 of socket1 determines the RAS mode of
the system. If the DIMM_A1 and DIMM_B1 are not identical, then the system falls back
to Independent Channel Mode.
