Intel E42249-003 Product Specification Download Page 102

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Intel

Server Board S5500BC TPS

Appendix B: Sensor Tables

Revision 1.0

Intel order number: E42249-003

Full Sensor Name

(Sensor name in SDR)

Sensor

Platform

Applicability

Sensor Type

Event /

Reading

Type

Event Offset

Triggers

Contrib. To

System Status

Assert /

De-

assert

Readable

Value /

Offsets

Event

Data

Rearm

Stand-

04 - Non-
redundant:
Sufficient
resources.
Transition from
insufficient.

Degraded

05 - Non-
redundant:
insufficient
resources.

Non-fatal

06 – Non-
Redundant:
degraded from
fully redundant.

Degraded

07 - Redundant
degraded from
non-redundant

Degraded

07 - Redundant
degrade from
non-redundant

Degraded

–

00 - Presence

As and

–

01 - Failure

Degraded

02 – Predictive
Failure

Degraded

03 - A/C lost

Degraded

Power Supply 1 Status

(PS/1 Status)

50h

Chassis-

specific

Power Supply

08h

Sensor

Specific

6Fh

06 –
Configuration
error

Trig

Offset

00 - Presence

As and

–

Power Supply 2 Status

(PS/2 Status)

51h

Chassis-

specific

Power Supply

08h

Sensor

Specific

6Fh

01 - Failure

Degraded

Trig

Offset

Summary of Contents for E42249-003

Page 1: ...Intel Server Board S5500BC Technical Product Specification Intel order number E42249 003 Revision 1 0 January 2009 Enterprise Platforms and Services Division Marketing...

Page 2: ...e definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Server Board S5500BC may contain design defects or errors know...

Page 3: ...Rules 17 3 1 3 Multiple Processor Initialization 19 3 1 4 Turbo Mode 20 3 1 5 Simultaneous Multi Threading 20 3 1 6 Enhanced Intel SpeedStep Technology 20 3 1 7 Multi Core Processor Support 21 3 1 8 I...

Page 4: ...3 4 8 Enhanced Power Management 33 3 4 9 System Management Interface 34 3 4 10 Real Time Clock RTC 34 3 4 11 Manageability 34 3 4 12 Unsupported Intel ICH10R Interfaces 34 3 5 Network Interface Contro...

Page 5: ...4 4 2 Command Bridging 49 4 4 3 External Communications Link 50 4 4 4 Alerting 50 4 4 5 System Information Passed to ME and POST Complete Notification 50 4 4 6 ACPI Mode Notification 51 4 4 7 Persist...

Page 6: ...0 8 2 4 Standby Outputs 71 8 2 5 Remote Sense 71 8 2 6 Voltage Regulation 71 8 2 7 Dynamic Loading 72 8 2 8 Capacitive Loading 72 8 2 9 Closed Loop Stability 72 8 2 10 Common Mode Noise 73 8 2 11 Ripp...

Page 7: ...9 3 5 BSMI Taiwan 83 9 3 6 RRL Korea 83 9 3 7 CNCA CCC China 83 Appendix A Integration and Usage Tips 84 Appendix B Sensor Tables 85 Appendix C POST Error Messages and Handling 94 Appendix D POST Cod...

Page 8: ...and Rubber Pad Keepout 12 Figure 10 Intel Light Guided Diagnostic LED Locations 13 Figure 11 External I O Layout 14 Figure 12 Functional Block Diagram 15 Figure 13 Intel IOH 5500 Chipset with Intel Q...

Page 9: ...15 RMM3 Connector Pin out J3C1 55 Table 16 Front Panel SSI Standard 24 pin Connector Pin out J9E2 56 Table 17 VGA Connector Pin out J7A1 57 Table 18 SATA Connector Pin out J1B4 J1B3 J1A2 J1B1 J1B2 an...

Page 10: ...tion Limits 72 Table 36 Transient Load Requirements 72 Table 37 Capacitive Loading Conditions 72 Table 38 Ripple and Noise 73 Table 39 Output Voltage Timing 74 Table 40 Turn On Off Timing 74 Table 41...

Page 11: ...List of Tables Intel Server Board S5500BC TPS Intel order number E42249 003 Revision 1 0 xii This page intentionally left blank...

Page 12: ...n peripherals and contain high density VLSI and power delivery components that need adequate airflow to cool Intel ensures through its own chassis development and testing that when Intel server buildi...

Page 13: ...onnector Two stacked RJ 45 connectors with Magnetics and LEDs and two USB combo connectors One external Serial Port Header 9 pin Two internal USB 2x5 pin headers each supports two USB 2 0 ports One 24...

Page 14: ...ee system fans USB Four USB 2 0 Ports connected to the Server Rear Panel Four USB 2 0 Ports connected to Headers on the motherboard One USB 1 1 Port connected to the Integrated BMC for KB MS function...

Page 15: ...1 0 4 2 2 Server Board Layout Figure 1 Intel Server Board S5500BC picture 2 2 1 Server Board Connector and Component Layout Figure 2 shows the board layout of the server board Each connector and majo...

Page 16: ...PCI 32 bit 33 MHz G Intel RMM3 slot H Slot 5 PCI Express x8 I Slot 6 PCI Express x8 Riser card J Slot 7 PCI Express x8 K Back panel I O ports L Diagnostic LEDs M Status LED N ID LED O External Serial...

Page 17: ...249 003 Revision 1 0 6 AA CPU Socket 2 BB CPU 2 fan header CC System fan 1 header DD DIMM sockets for Channel D and E Supports CPU_2 EE SATA SGPIO FF SATA 0 GG SATA 1 HH SATA 2 2 2 2 Server Board Mech...

Page 18: ...Intel Server Board S5500BC TPS Product Overview Revision 1 0 Intel order number E42249 003 7 Figure 4 Mounting hole location...

Page 19: ...Product Overview Intel Server Board S5500BC TPS Intel order number E42249 003 Revision 1 0 8 Figure 5 Major connector pin 1 locations...

Page 20: ...Intel Server Board S5500BC TPS Product Overview Revision 1 0 Intel order number E42249 003 9 Figure 6 S5500BC Board Primary Side Keepouts...

Page 21: ...Product Overview Intel Server Board S5500BC TPS Intel order number E42249 003 Revision 1 0 10 Figure 7 S5500BC Board PRIMARY SIDE CARD SIDE KEEPOUT ZONE...

Page 22: ...Intel Server Board S5500BC TPS Product Overview Revision 1 0 Intel order number E42249 003 11 Figure 8 Secondary Side Keepout Mounting Hole Keepout...

Page 23: ...Product Overview Intel Server Board S5500BC TPS Intel order number E42249 003 Revision 1 0 12 Figure 9 Secondary Side Keepout CPU Socket and Rubber Pad Keepout...

Page 24: ...Intel Light Guided Diagnostic LED Locations Table 2 Intel Light Guided Diagnostic LED reference Description Description A Post Code Diagnostic LEDs B Status LED C System ID LED D HDD LED E System Fan...

Page 25: ...number E42249 003 Revision 1 0 14 2 2 4 External I O Connector Locations Figure 11 External I O Layout Table 3 External I O Layout Reference Description Description A Serial Port A B Video C USB Port...

Page 26: ...ipset component and the architectural blocks that make up this server board Figure 12 Functional Block Diagram 3 1 Processor Sub system The Intel Xeon processor 5500 series is the first generation ser...

Page 27: ...tion The Intel IOH 5500 chipset supports up to two processor sockets with up to four cores per socket With Intel QuickPath Interconnect caching agents are responsible for participating in the cache co...

Page 28: ...eled CPU_1 A terminator is not required in the second processor socket when a single processor is used When two processors are installed the following population rules apply Both processors must be fr...

Page 29: ...ven for the error The error is logged to the error manager Table 5 Mixed Processor Configurations Error Severity System Action Processor family not Identical Fatal The BIOS detects the error condition...

Page 30: ...r Pauses the system for user intervention Processor Intel QuickPath Interconnect speeds not identical Fatal The BIOS detects the error condition and responds as follows Logs the error into the system...

Page 31: ...Turbo Mode operates under operating system control only entered when the operating system requests higher performance such as a transition from a P1 state to a P0 state Ability to enter Turbo Mode is...

Page 32: ...the board The unified back plate for dual processor server products consists of a flat steel back plate with threaded studs for ILM attachment and internally threaded nuts for attaching the heat sink...

Page 33: ...and URS 3 2 Memory Sub system 3 2 1 Integrated Memory Controller The Intel Xeon processors 5500 series has an Integrated Memory Controller IMC The Intel Server Board S5500BC memory interface supports...

Page 34: ...ty availability and serviceability mode of operation 3 2 2 DIMM Population Requirements DIMMs on this board are organized into physical slots on the DDR3 memory channels divided between two processor...

Page 35: ...nnel mode Therefore DIMM_A2 cannot be populated used if DIMM_A1 is empty When CPU socket 1 is empty any DIMM memory in channel A and B is unavailable When CPU socket 2 is empty any DIMM memory in chan...

Page 36: ...l operate at the maximum common frequency You can use Independent Channel Mode to support a single DIMM configuration in channel A and Single Channel Mode You should observe the following general rule...

Page 37: ...e highest common frequency of all DDR3 DIMMs 3 2 5 CPU Cores QPI Links and DDR3 Channels Frequency Configuration The Intel Xeon processor 5500 series connects to each other and to the Intel IOH 5500 c...

Page 38: ...ECC DIMMs be populated Independent Mode is the only mode that supports non ECC DIMMs in addition to ECC DIMMs 3 2 7 Independent Channel Mode You can populate channels in any order in Independent Chan...

Page 39: ...processors The following table shows the features supported by the chipset Table 7 Intel IOH 5500 Chipset Features Chipset Intel QuickPath Interconnect Ports Processor PCI Express Lanes Manageability...

Page 40: ...the ICH The Management Engine ME resides in the IOH and communicates with the ICH LAN Controller through this interface 3 3 4 Management Engine ME The Management Engine ME is an embedded ARC controlle...

Page 41: ...other SPS features are not functional when the update is in progress 3 3 4 2 Management Engine Interaction ME BMC interactions include the following BMC stores sensor data records for ME owned sensors...

Page 42: ...R The Intel ICH10R I O Controller Hub provides extensive I O support Functions and capabilities include PCI Express Base Specification Revision 1 1 support PCI Local Bus Specification Revision 2 3 for...

Page 43: ...tions on the Advanced Mass Storage Controller Configuration setup page some of which affect the ability to configure RAID The Onboard SATA Controller option is enabled by default When this option is e...

Page 44: ...ow speed signaling The Intel ICH10R supports up to 12 USB 2 0 ports All 12 ports are high speed full speed and low speed capable Intel ICH10R s port routing logic determines whether a USB port is cont...

Page 45: ...the Intel Server Board S5500BC Keeps track of the time of day Stores System configuration data even when the system is powered down The RTC operates on a 32 768 KHz crystal and a 3 V lithium battery...

Page 46: ...ates to the NIC1 connector on the back edge of the board When looking at the I O panel the NIC 1 should be wired to the left most RJ 45 connector The Intel 82574L GbE Ethernet Controller and the exter...

Page 47: ...100BASE TX and 1000BASE T 802 3 802 3u and 802 3ab applications NC SI or SMBus connection to a Manageability Controller MC IEEE 1149 1 JTAG Support for PCI 3 0 Vital Product Data VPD IPMI MC pass thr...

Page 48: ...is platform dependant The Integrated BMC on the Intel Server Board S5500BC contains the following integrated functionality Server Class Super I O functionality includes Keyboard Style BT interface fo...

Page 49: ...ndom Number generator JTAG Master interface On Chip Test Infrastructure for testing BMC firmware Remote KVMS Features USB 2 0 interface for Keyboard Mouse and Remote storage such as a CD DVD ROM and f...

Page 50: ...This interface is available from either of available NIC ports in system which can be shared with the host Only one NIC may be enabled for management traffic at any time The active interface is NIC2...

Page 51: ...the 2D modes supported for both CRT and LCD Table 9 Video Modes 2D Video Mode Support 2D Mode Refresh Rate Hz 8 bpp 16 bpp 32 bpp 640x480 60 72 75 85 90 100 120 160 200 Supported Supported Supported 8...

Page 52: ...stem Wake from S1 is supported on LAN USB Serial port and PCI Express slots Wake from S4 are supported on LAN Serial Port Front panel Power button and potentially RTC To save power consumption during...

Page 53: ...ng system power control thermal monitoring and management including system fan control The BMC provides system interface and monitoring features based on the IPMI 2 0 specification This section provid...

Page 54: ...Intel Server Board S5500BC TPS Platform Management Revision 1 0 Intel order number E42249 003 43 Figure 18 SMBUS Block Diagram...

Page 55: ...sensor scanning monitoring The BMC provides IPMI management of sensors It polls sensors to monitor and report system health IPMI interfaces Host interfaces include system management software SMS with...

Page 56: ...DIMM temperature monitoring New sensors and improved acoustic management using closed loop fan control algorithm taking into account DIMM temperature readings Address Resolution Protocol ARP The BMC s...

Page 57: ...power loss 4 2 3 Media Redirection The embedded web server provides a Java applet to enable remote media redirection This may be used in conjunction with the remote KVM feature or as a standalone appl...

Page 58: ...rvices for Management WS MAN The BMC firmware supports the Web Services for Management WS MAN specification 4 2 6 Local Directory Authentication Protocol LDAP The BMC firmware supports the Local Direc...

Page 59: ...irection normally ends at the beginning of the legacy OS boot INT 19h The operating system is responsible for continuing the redirection from that point unless the legacy operating system redirection...

Page 60: ...n on Serial A Legacy Console Redirection The BIOS enables Legacy OS redirection on Serial A or Serial B depending upon the BIOS settings Legacy OS redirection happens at the same Baud Flow Control and...

Page 61: ...for NPTM management but do not represent significant fault conditions and do not need to be entered in the SEL are sent to the BMC using the IPMI Alert Immediate command This requires the external SW...

Page 62: ...nt operating system is running 4 4 7 Persistence Across Boots Data passed to the ME will persist across boots but will not persist across AC power loss 4 5 Power Management Bus PMBUS The BMC firmware...

Page 63: ...IO 1 J1C1 Header 4 IPMB 2 J8B1 Header 4 HSBP 1 J9B1 Header 4 Fans 5 J3K1 J7K2 J3K2 J8K3 J8B4 Header 4x5 RMM3 1 J3C1 RMM3 connector 34 Power Supply 3 J9B3 J7K1 J9E1 Header 24 8 5 USB 4 J1A3 J2A2 J5A1 J...

Page 64: ...Signal Name Color 1 3 3V Orange 13 3 3V Orange 2 3 3V Orange 14 12V Blue 3 GND Black 15 GND Black 4 5V Red 16 PS_ON Green 5 GND Black 17 GND Black 6 5V Red 18 GND Black 7 GND Black 19 GND Black 8 PWR_...

Page 65: ...file PCI Riser Card Pin out J3C1 Pin Name Slot Name Pin B1 12V PRSNT1 A1 B2 12V 12V A2 B3 12V 12V A3 B4 GND GND A4 B5 SMCLK JTAG2 A5 B6 SMDATA JTAG3 A6 B7 GND INTRU A7 B8 3 3V JTAG5 A8 B9 JTAG1 3 3V A...

Page 66: ...ed BMC with an additional dedicated network interface The dedicated interface uses a separate LAN channel The RMM3 provides additional flash storage for advanced features such as the WS MAN The follow...

Page 67: ...SI Standard 24 pin Connector Pin out J9E2 Pin Signal Name Control Panel Pin out Pin Signal Name 1 P3V3_STBY 2 P3V3_STBY 3 Key 4 P5V_STBY 5 FP_PWR_LED_N_R 6 FP_ID_LED_R1_N 7 P3V3 HDD Activity LED Anode...

Page 68: ...DDCCLK 5 6 2 SATA II Connectors The Intel Server Board S5500BC provides six Serial ATA connectors J1B4 J1B3 J1A2 J1B1 J1B2 and J2B1 Table 18 SATA Connector Pin out J1B4 J1B3 J1A2 J1B1 J1B2 and J2B1 Pi...

Page 69: ...s for each Table 19 9 pin External Serial A Port Header Pin out J8A1 Pin Signal Name Description 1 SPA_DCD 2 SPA_SIN_N 3 SPA_SOUT_N 4 SPA_DTR 5 GND 6 SPA_DSR 7 SPA_RTS 8 SPA_CTS 9 SPA_RI Table 20 Inte...

Page 70: ..._C 20 GRN_A 21 GRN_C YEL_A 22 GRN_A YEL_C Four ports are connected to the two 2x5 headers J1A3 J2A2 on the Intel Server Board S5500BC The following table provides the pin out information for the heade...

Page 71: ...d 2 12V Power Power supply 12 V 3 Fan Tach Out FAN_TACH signal is connected to the BMC to monitor the fan speed 4 Fan PWM In FAN_PWM signal to control the fan speed Note The Intel Server Board S5500BC...

Page 72: ...is provided This is intended to support micro switches that close making a connection to ground when the chassis is opened or removed The intrusion signal is routed to the Integrated BMC internal int...

Page 73: ...order number E42249 003 Revision 1 0 62 5 11 SATA RAID Key Header Table 27 SATA connector Pin out J7B1 Pin Signal Name 1 GND 2 FM_ICH_RAID_KEY 3 GND 5 12 IPMB Header Table 28 IPMB Connector Pin out J...

Page 74: ...2 BMC Firmware Force Update Mode Disabled Default J8C1 BMC Force Update 2 3 BMC Firmware Force Update Mode Enabled 1 2 These pins should have a jumper in place for normal system operation Default J2D...

Page 75: ...hould have a jumper in place for normal system operation Default J1A1 BIOS Recovery 2 3 The main system BIOS will not boot with these pins jumpered Note The system will boot from EFI bootable recovery...

Page 76: ...can be illuminated using either of two mechanisms By pressing the system ID button on the system control panel the ID LED displays a solid blue color until the button is pressed again By issuing the a...

Page 77: ...atal Non fatal alarm system is likely to fail CATERR asserted Critical temperature threshold asserted Critical voltage threshold asserted Critical fan threshold asserted VRD hot asserted SMI Timeout a...

Page 78: ...cutes several platform configuration processes with specific hex POST code numbers As each configuration routine is started the BIOS displays the POST code on the POST code diagnostic LEDs on the back...

Page 79: ...18 inches 12 inches 9 inches Vibration unpackaged 5 Hz to 500 Hz 3 13 random Note Intel Server Boards support add in peripherals and contain a number of high density VLSI and power delivery components...

Page 80: ...Intel Server Board S5500BC TPS Power and Environmental Specifications Revision 1 0 Intel order number E42249 003 69 Figure 20 Power Distribution Block Diagram...

Page 81: ...conditions with peripherals is about 80 of the total worst case power dissipation or 503 W This includes a 15 regulator efficiency 8 2 2 Turn On No Load Operation At power on the system should present...

Page 82: ...late out drops in the system for the 3 3 V output The 5 V 12 V1 12 V2 12 V3 12 V and 5 VSB outputs only use remote sense referenced to the ReturnS signal The remote sense input impedance to the power...

Page 83: ...MIN load to the MAX load conditions Table 36 Transient Load Requirements Output Step Load Size 1 Load Slew Rate Test Capacitive Load 3 3 V 6 0 A 0 25 A sec 250 F 5 V 4 0 A 0 25 A sec 400 F 12 V 18 0 A...

Page 84: ...y output connectors A 10 F tantalum capacitor in parallel with a 0 1 F ceramic capacitor are placed at the point of measurement Table 38 Ripple and Noise 3 3 V 5 V 12 V 12 V 5 VSB 50mVp p 50mVp p 120m...

Page 85: ...23 V out V1 V2 V3 V4 Tvout_on Tvout_rise 10 V out Tvout_off Figure 21 Output Voltage Timing Table 40 Turn On Off Timing Item Description Minimum Maximum Units Tsb_on_delay Delay from AC applied to 5VS...

Page 86: ...PWOK 5 VSB PSON AF001024 Tvout_holdup TAC_on_delay Tsb_on_delay Tpwok_on AC turn on off cycle PSON turn on off cycle Tsb_vout T5VSB_holdup Tpwok_holdup Tpwok_off Tpwok_low Tpson_on_delay Tsb_on_delay...

Page 87: ...s an FCC Class A device Integration of it into a Class B chassis does not result in a Class B device 9 1 Product Regulatory Compliance Intended Application This product was evaluated as Information Te...

Page 88: ...roduct having insufficient protection against electromagnetic effects which may cause improper operation of the product 9 1 3 Certifications Registrations Declarations UL Certification US Canada CE De...

Page 89: ...substances are noted below Quantity limit of 0 1 by mass 1000 PPM for Lead Mercury Hexavalent Chromium Polybrominated Biphenyls Diphenyl Ethers PBB PBDE Quantity limit of 0 01 by mass 100 PPM for Cadm...

Page 90: ...S A D33025 BSMI Marking Class A Taiwan C tick Marking Australia New Zealand N232 RRL MIC Mark Korea CPU Model Name A Country of Origin Exporting Requirements MADE IN xxxxx Provided by label not silk s...

Page 91: ...rked on packaging label Other Recycling Package Marks Other Recycling Package Marking Marked on packaging label CA Lithium Perchlorate insert Perchlorate Material Special handling may apply See www dt...

Page 92: ...e with the instructions may cause harmful interference to radio communications However there is no guarantee that interference will not occur in a particular installation If this equipment does cause...

Page 93: ...the interference causing equipment standard entitled Digital Apparatus ICES 003 of the Canadian Department of Communications 9 3 3 Europe CE Declaration of Conformity This product has been tested in...

Page 94: ...r Korea English translation of the notice above 1 Type of Equipment Model Name On License and Product 2 Certification No On RRL certificate Obtain certificate from local Intel representative 3 Name of...

Page 95: ...ion will perform better than a One DIMM configuration In a Two DIMM configuration DIMMs should be installed in DIMM sockets A1 and D1 An Eight DIMM configuration DIMM sockets A1 B1 A2 B2 D1 D2 E1 and...

Page 96: ...t only have two states Event Thresholds Triggers The following event thresholds are supported for threshold type sensors u l nr c nc upper non recoverable upper critical upper non critical lower non r...

Page 97: ...icates the type supported by the sensor The following abbreviations are used in the comment column to describe a sensor A Auto rearm M Manual rearm I Rearm by init agent Default Hysteresis Hysteresis...

Page 98: ...01h All Power Unit 09h Sensor Specific 6Fh 05 Soft power control failure 06 Power unit failure Fatal Trig Offset A X 00 Fully Redundant OK As and De 01 Redundancy lost Degraded 02 Redundancy degraded...

Page 99: ...e X Physical Security Physical Scrty 04h Chassis Intrusion is chassis specific Physical Security 05h Sensor Specific 6Fh 04 LAN leash lost OK Trig Offset A FP Interrupt FP NMI Diag Int 05h Chassis spe...

Page 100: ...1 8V AUX 15h All Voltage 02h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analog R T A X BB 3 3V BB 3 3V 16h All Voltage 02h Threshold 01h u l c nc nc Degraded c Non fatal As and De Analo...

Page 101: ...Mem P1 Thrm Mrgn 23h All Temperature 01h Threshold 01h u c nc nc Degraded c Non fatal As and De Analog R T A Processor 2 Memory Thermal Margin Mem P2 Thrm Mrgn 24h Dual processor only Temperature 01h...

Page 102: ...05 Non redundant insufficient resources Non fatal 06 Non Redundant degraded from fully redundant Degraded 07 Redundant degraded from non redundant Degraded 07 Redundant degrade from non redundant Degr...

Page 103: ...urr Out 54h Chassis specific Current 03h Threshold 01h u c nc nc Degraded c Non fatal As and De Analog R T A X Power Supply 2 12V of Maximum Current Output PS 2 Curr Out 55h Chassis specific Current 0...

Page 104: ...ermal Control P2 Therm Ctrl 65h Dual processor only Temperature 01h Threshold 01h u c nc nc Degraded c Non fatal As and De Analog Trig Offset A Processor 1 VRD Temp P1 VRD Hot 66h All Temperature 01h...

Page 105: ...ed to the SEL The setup POST error Pause setting determines whether the system pauses to the Error Manager for this type of error where the user can take immediate corrective action or choose to conti...

Page 106: ...st BIST Major 852C DIMM_D1 failed Self Test BIST Major 852D DIMM_D2 failed Self Test BIST Major 852E DIMM_D3 failed Self Test BIST Major 8540 DIMM_A1 Disabled Major 8541 DIMM_A2 Disabled Major 8542 DI...

Page 107: ...ncountered Major 85A5 DIMM_B2 Uncorrectable ECC error encountered Major 85A6 DIMM_B3 Uncorrectable ECC error encountered Major 85A8 DIMM_C1 Uncorrectable ECC error encountered Major 85A9 DIMM_C2 Uncor...

Page 108: ...2 TPM device failure Minor 0xA003 TPM device failed self test Minor 0xA022 Processor component encountered a mismatch error Major 0xA027 Processor component encountered a low voltage error Minor 0xA02...

Page 109: ...Intel order number E42249 003 Revision 1 0 98 The user can override this option by setting the POST Error Pause option as disabled on the BIOS setup Main screen If this option is disabled the system b...

Page 110: ...nibble bits are represented by Diagnostics LEDs 0 1 2 and 3 Given the bit is set in the upper and lower nibbles and then the corresponding LED is lit If the bit is clear corresponding LED is off Diag...

Page 111: ...locating resources to PCI buses 0x52h X O X O X X O X Hot Plug PCI controller initialization 0x53h X O X O X X O O Reserved for PCI bus 0x54h X O X O X O X X Reserved for PCI bus 0x55h X O X O X O X O...

Page 112: ...device selection 5 0xD6 O O X O X O O X Trying to boot device selection 6 0Xd7 O O X O X O O O Trying to boot device selection 7 0xD8 O O X O O X X X Trying to boot device selection 8 0xD9 O O X O O...

Page 113: ...has been called Pre EFI Initialization Module PEIM Recovery 0x30h X X O O X X X X Crisis recovery has been initiated because of a user request 0x31h X X O O X X X O Crisis recovery has been initiated...

Page 114: ...C The server board and the system have features designed to support the high density server market For more information refer to the Intel Server System SR1630BC Technical Product Specification TPS A...

Page 115: ...with two power factor correction PFC power supply unit PSU configurations SC5650DP 600 W fixed PSU for dual processor server boards SC5650BRP 600 W 1 1 redundant PSU for dual processor server boards F...

Page 116: ...Enabling Kit CHAP Challenge Handshake Authentication Protocol CMOS In terms of this specification this describes the PC AT compatible region of battery backed 128 bytes of memory which normally resid...

Page 117: ...M Original Equipment Manufacturer Ohm Unit of electrical resistance PEF Platform Event Filtering PEP Platform Event Paging PIA Platform Information Area This feature configures the firmware for the pl...

Page 118: ...k Management Protocol TBD To Be Determined TIM Thermal Interface Material UART Universal Asynchronous Receiver Transmitter UDP User Datagram Protocol UHCI Universal Host Controller Interface UTC Coord...

Page 119: ...tion Intel S5500 Chipset I O Hub IOH 36D 24D External Design Specification Intel Xeon Processor 5500 Series and LGA1366 Socket Thermal Mechanical Design Guide Intel Xeon Processor 5500 Series External...

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