Intel
®
Server Board S5500BC TPS
Functional Architecture
Revision 1.0
Intel order number: E42249-003
27
The Intel
®
Xeon
®
processor 5500 series offer memory RAS at the channel level. Mirroring
occurs at the channel level. Channel B mirrors channel A. All DIMM matching requirements are
on a slot-to-slot basis on adjacent channels. To enable Mirroring, the corresponding slots on
channel A and channel B must have DIMMs with identical parameters. DIMMs on adjacent slots
on the same channel are not required to have identical parameters.
When installing memory, you must populate first the memory slot that is the farthest away in the
channel for each processor (See “Channel Slots Configuration” figure), even for Independent
Channel mode. Therefore, you cannot populate/use DIMM_A2 if DIMM_A1 is empty.
The Intel
®
Xeon
®
processor 5500 series on socket 1 and socket 2 in a dual processor
configuration is completely autonomous. DIMMs routed to sockets are isolated and can be
initialized locally, including RAS configurations. The Intel
®
Server Board S5500BC provides one
set of RAS questions in the BIOS Setup and can configure common RAS features across the
sockets. If one socket fails the RAS population requirements, the BIOS sets all channels to
Independent Channel mode. The rules on channel population and channel matching vary by the
RAS mode used. Note that support of RAS modes require matching DIMM population between
channels (sparing, mirroring, and lockstep) require that ECC DIMMs be populated. Independent
Mode is the only mode that supports non-ECC DIMMs in addition to ECC DIMMs.
3.2.7
Independent Channel Mode
You can populate channels in any order in Independent Channel Mode. You can populate both
channels in any order and have no matching requirements. All channels must run at the same
interface frequency, but individual channels may run at different DIMM timings (RAS latency,
CAS latency, and so forth).
3.2.8
Channel Mirroring Mode
The Intel
®
Xeon
®
processor 5500 series supports channel mirroring to configure the available
channels of DDR3 DIMMs in a mirrored configuration. Unlike channel sparing, the mirrored
configuration is a redundant image of the memory and can continue to operate when sporadic
uncorrectable errors occur.
3.2.9
Lockstep Channel Mode
In Lockstep Channel Mode, each memory access is a 128-bit data access that spans the first
channel and the second channel. The same address is used on both channels such that an
address error on any channel is detectable by bad ECC. Lockstep channel mode requires that
you populate the first channel and the second channel identically. That is, each DIMM in one
channel must have a corresponding DIMM of identical organization such as the number of
ranks, banks, rows, and/or columns. DIMMs may be of different speed grades, but the Intel
®
QuickPath Memory Controller is configured to operate all DIMMs according to the slowest
parameters present. DIMM slot populations within a channel do not have to be identical, but the
same DIMM slot location across the first channel and the second channel must be populated
the same. The third channel is unused in lockstep channel mode.
