Functional Architecture
Intel
®
Server Board S5500BC TPS
Intel order number: E42249-003
Revision 1.0
24
The DIMM identifiers on the silkscreen on the board provide information about which
channel and therefore which node they belong to. For example, DIMM_A1 is the first slot
on channel A of node 1. DIMM_D1 is the first DIMM socket on channel D of node 2.
The memory slots for each DDR3 channel from the Intel
®
Xeon
®
5500 processor series
must be populated on a farthest first fashion. This also holds true for Independent
Channel mode. Therefore, DIMM_A2 cannot be populated/used if DIMM_A1 is empty.
When CPU socket 1 is empty, any DIMM memory in channel A and B is unavailable.
When CPU socket 2 is empty, any DIMM memory in channel D and E is unavailable.
If channel A and channel B are empty, CPU socket 1 can still function if memory is
available from channel D and channel E. However, platform performance will suffer
latency due to remote memory.
Sockets are self-contained and autonomous. However, all RAS Error Management
configurations in the BIOS setup will be applied commonly across sockets.
Figure 16. Channel slots Configuration
The DIMM population configurations (UDIMMs or RDIMMs) for two slots per channel are
reviewed in the following table.
