Summary Tables of Changes
R
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
11
NO. E0 nC1 nD1 Plans
ERRATA
AC28 X
Fixed
Multiple accesses to the same S-state L2 cache line and ECC
error combination may result in loss of cache coherency
AC29
X
Fixed
Processor may hang when resuming from Deep Sleep state
AC30 X X X NoFix
When the processor is in the System Management Mode
(SMM), debug registers may be fully writeable
AC31 X X X NoFix
Associated counting logic must be configured when using
Event Selection Control (ESCR) MSR
AC32 X X X NoFix
IA32_MC0_ADDR and IA32_MC0_MISC registers will contain
invalid or stale data following a Data, Address, or Response
Parity Error
AC33 X
Fixed
CR2 may be incorrect or an incorrect page fault error code
may be pushed onto stack after execution of an LSS
instruction
AC34 X X X NoFix
System may hang if a fatal cache error causes Bus Write Line
(BWL) transaction to occur to the same cache line address as
an outstanding Bus Read Line (BRL) or Bus Read-Invalidate
Line (BRIL)
AC35 X
Fixed
Processor Does not Flag #GP on Non-zero Write to Certain
MSRs
AC36
X
Fixed
L2 cache may contain stale data in the Exclusive state
AC37 X X X NoFix
Simultaneous assertion of A20M# and INIT# may result in
incorrect data fetch
AC38
S
X X X NoFix
Glitches on Address and Data Strobe Signals May Cause
System Shutdown
AC39
X
Fixed
CPUID Returns Incorrect Number of ITLB Entries
AC40 X X X NoFix
A Write to an APIC Register Sometimes May Appear to Have
Not Occurred
AC41 X Fixed
Store to Load Data Forwarding may Result in Switched Data
Bytes
AC42 X X NoFix
Parity Error in the L1 Cache may Cause the Processor to
Hang
AC43 X Fixed
The TCK Input in the Test Access Port (TAP) is Sensitive to
Low Clock Edge Rates and Prone to Noise Coupling Onto
TCK's Rising or Falling Edges
AC44 X X
Fixed
Re-mapping the APIC base address to a value less than or
equal to 0xDC001000 may cause IO and Special Cycle failure
AC45
X
X
Fixed
Erroneous BIST result found in EAX register after reset
AC46 X X X NoFix
The State of the Resume Flag (RF Flag) in a Task-State
Segment (TSS) May be Incorrect
AC47 X X X NoFix
Changes to CR3 Register do not Fence Pending Instruction
Page Walks
AC48 X X X NoFix
Processor Provides a 4-Byte Store Unlock After an 8-Byte
Load Lock
