Errata
R
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
35
AC41.
Store to Load Data Forwarding may Result in Switched Data Bytes
Problem:
If in a short window after an instruction that updates a segment register has executed, but has not
yet retired, there is a load occurring to an address, that matches a recent previous store operation,
but the data size is smaller than the size of the store, the resulting data forwarded from the store to
the load may have some of the lower bytes switched
.
Implication:
If this erratum occurs, the processor may execute with incorrect data.
Workaround:
It is possible for the BIOS to contain a workaround for this erratum.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC42.
Parity Error in the L1 Cache May Cause the Processor to Hang
Problem:
If a locked operation accesses a line in the L1 cache that has a parity error, it is possible that the
processor may hang while trying to evict the line.
Implication:
If this erratum occurs, it may result in a system hang. Intel has not observed this erratum with any
commercially available software
Workaround:
None
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC43.
The TCK Input in the Test Access Port (TAP) Is Sensitive to Low Clock
Edge Rates and Prone to Noise Coupling onto TCK's Rising or Falling
Edges
Problem:
TCK is susceptible to double clocking when low amplitude noise occurs on TCK edge, while it is
crossing the receiver's transition region. TAP failures tend to increase with increases in
background system noise.
Implication:
This only impacts JTAG/TAP accesses to the processor. Other bus accesses are not affected.
Workaround:
To minimize the effects of this issue, reduce noise on the TCK-net at the processor relative to
ground, and position TCK relative to BCLK to minimize the TAP error rate. Decreasing rise
times to under 800 ps reduces the failure rate but does not stop all failures.
Status:
For the steppings affected, see the
Summary Tables of Changes.
