Errata
R
36
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC44.
Re-Mapping the APIC Base Address to a Value Less Than or Equal to
0xDC001000 May Cause IO and Special Cycle Failure
Problem:
Remapping the APIC base address from its default can cause conflicts with either I/O or special
cycle bus transactions.
Implication:
Either I/O or special cycle bus transactions can be redirected to the APIC, instead of appearing on
the front-side bus.
Workaround:
Use any APIC base addresses above 0xDC001000 as the relocation address.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC45.
Erroneous BIST Result Found in EAX Register after Reset
Problem:
The processor may show an erroneous BIST (built-in self test) result in the EAX register bit 0
after coming out of reset.
Implication:
When this erratum occurs, an erroneous BIST failure will be reported in the EAX register bit 0,
however this failure can be ignored since it is not accurate.
Workaround:
It is possible for BIOS to workaround this issue by masking off bit 0 in the EAX register where
BIST results are written.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC46.
The State of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May
Be Incorrect
Problem:
After executing a JMP instruction to the next (or other) task through a hardware task switch, it is
possible for the state of the RF flag (in the EFLAGS register image) to be incorrect.
Implication:
The RF flag is normally used for code breakpoint management during debug of an application. It
is not typically used during normal program execution. Code breakpoints or single step debug
behavior in the presence of hardware task switches, therefore, may be unpredictable as a result of
this erratum. This erratum has not been observed in commercially available software.
Workaround:
None
Status:
For the steppings affected, see the
Summary Tables of Changes
.
