Errata
R
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
21
AC6.
FSW May Not Be Completely Restored after Page Fault on FRSTOR or
FLDENV Instructions
Problem:
If the FPU operating environment or FPU state (operating environment and register stack) being
loaded by an FLDENV or FRSTOR instruction wraps around a 64-Kbyte or 4-Gbyte boundary
and a page fault (#PF) or segment limit fault (#GP or #SS) occurs on the instruction near the wrap
boundary, the upper byte of the FPU status word (FSW) might not be restored. If the fault handler
does not restart program execution at the faulting instruction, stale data may exist in the FSW.
Implication:
When this erratum occurs, stale data will exist in the FSW.
Workaround:
Ensure that the FPU operating environment and FPU state do not cross 64Kbyte or 4Gbyte
boundaries. Alternately, ensure that the page fault handler restarts program execution at the
faulting instruction after correcting the paging problem.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC7.
The Processor Flags #PF Instead of #AC on an Unlocked CMPXCHG8B
Instruction
Problem:
If a data page fault (#PF) and alignment check fault (#AC) both occur for an unlocked
CMPXCHG8B instruction, then #PF will be flagged.
Implication:
Software that depends #AC before #PF will be affected since #PF is flagged in this case.
Workaround:
Workaround: Remove the software’s dependency on the fact that #AC has precedence over #PF.
Alternately, reload the page in the page fault handler and then restart the faulting instruction.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC8.
When in No-Fill Mode the Memory Type of Large Pages Are Incorrectly
Forced to Uncacheable
Problem:
When the processor is operating in No-Fill Mode (CR0.CD=1), the paging hardware incorrectly
forces the memory type of large (PSE-4M and PAE-2M) pages to uncacheable (UC) memory type
regardless of the MTRR settings. By forcing the memory type of these pages to UC, load
operations, which should hit valid data in the L1 cache, are forced to load the data from system
memory. Some applications will lose the performance advantage associated with the caching
permitted by other memory types
Implication:
This erratum may result in some performance degradation when using no-fill mode with large
pages.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
