Intel Celeron Series, Specification

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Summary Tables of Changes
R
12 Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
NO. E0 nC1 nD1 Plans ERRATA
AC49 X X X NoFix
System Bus Interrupt Messages Without Data Which Receive
a HardFailure Response May Hang the Processor
AC50 X X X NoFix
Memory Type of the Load Lock Different from its
Corresponding Store Unlock
AC51 X X X NoFix
A 16-bit Address Wrap Resulting from a Near Branch (Jump or
Call) May Cause an Incorrect Address to Be Reported to the
#GP Exception Handler
AC52 X X NoFix
ITP Cannot Continue Single Step Execution after the First
Breakpoint
AC53 X X PlanFix
PWRGOOD and TAP Signals Maximum Input Hysteresis
Higher Than Specified
AC54 X X NoFix
Incorrect Debug Exception (#DB) May Occur When a Data
Breakpoint is set on an FP Instruction
AC55 X X X NoFix xAPIC May Not Report Some Illegal Vector Errors
AC56 X PlanFix
A Timing Marginality in the Instruction Decoder Unit May
Cause an Unpredictable Application Behavior and/or System
Hang
AC57 X X X NoFix
Memory Aliasing of Pages as Uncacheable Memory Type and
Write Back (WB) May Hang the System
AC58 X X NoFix
Using STPCLK and Executing Code From Very Slow Memory
Could Lead to a System Hang
AC59 X X X No Fix
Machine Check Exceptions May not Update Last-Exception
Record MSRs (LERs)
AC60 X X No Fix
Stores to Page Tables May Not Be Visible to Pagewalks for
Subsequent Loads Without Serializing or Invalidating the Page
Table Entry
AC61 X PlanFix
A Timing Marginality in the Arithmetic Logic Unit (ALU) May
Cause Indeterminate Behavior
AC62 X X X NoFix
With TF (Trap Flag) Asserted, FP Instruction That Triggers an
Unmasked FP Exception May Take Single Step Trap Before
Retirement of Instruction
AC63 X X X PlanFix
BTS(Branch Trace Store) and PEBS(Precise Event Based
Sampling) May Update Memory outside the BTS/PEBS Buffer
AC64 X X X NoFix
Memory Ordering Failure May Occur with Snoop Filtering
Third Party Agents after Issuing and Completing a BWIL (Bus
Write Invalidate Line) or BLW (Bus Locked Write) Transaction
AC65 X X X NoFix
Control Register 2 (CR2) Can be Updated during a REP
MOVS/STOS Instruction with Fast Strings Enabled
AC66 X X X NoFix
Writing the Local Vector Table (LVT) when an Interrupt is
Pending May Cause an Unexpected Interrupt
AC67 X X X NoFix
Using 2M/4M Pages When A20M# Is Asserted May Result in
Incorrect Address Translations
AC68 X X X NoFix
Writing Shared Unaligned Data that Crosses a Cache Line
without Proper Semaphores or Barriers May Expose a
Memory Ordering Issue