Errata
R
20
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC3.
Uncacheable (UC) Code in Same Line As Write Back (WB) Data May Lead to
Data Corruption
Problem:
When both code (being accessed as UC or WC) and data (being accessed as WB) are aliased into
the same cache line, the UC fetch will cause the processor to self-snoop and generate an implicit
writeback. The data supplied by this implicit writeback may be corrupted due to the way the
processor handles self-modifying code.
Implication:
UC or WC code located in the same cache line as WB data may lead to data corruption.
Workaround:
UC or WC code should not be located in the same physical 64-byte cache line as any location that
is being stored to with WB data
Status:
For the steppings affected, see the
Summary Tables of Changes
.
AC4.
Transaction Is Not Retried after BINIT#
Problem:
If the first transaction of a locked sequence receives a HITM# and DEFER# during the snoop
phase it should be retried and the locked sequence restarted. However, if BINIT# is also asserted
during this transaction, it will not be retried.
Implication:
When this erratum occurs, locked transactions will unexpectedly not be retried.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC5.
Invalid Opcode 0FFFh Requires a ModRM Byte
Problem:
Some invalid opcodes require a ModRM byte (or other following bytes), while others do not. The
invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel® architecture
processors, but does in the Intel® Pentium® 4 processor.
Implication:
The use of an invalid opcode 0FFFh without the ModRM byte may result in a page or limit fault
on the Pentium 4 processor.
Workaround:
Use a ModRM byte with invalid 0FFFh opcode.
Status:
For the steppings affected, see the
Summary Tables of Changes.
