Intel Celeron Series Specification Download Page 9

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Summary Tables of Changes

Intel

Celeron

Processor in the 478-Pin Package Specification Update

Note:

Each Specification Update item is prefixed with a capital letter to distinguish the product. The key

below details the letters that are used in Intel’s microprocessor Specification Updates:

A = Dual-Core Intel® Xeon® processor 7000 sequence

B = Mobile Intel ® Pentium ® II processor

C = Intel ® Celeron ® processor

E = Intel ® Pentium ® III processor

F = Intel® Pentium®

processor Extreme Edition

and Intel® Pentium® D

processor

G = Intel ® Pentium ® III Xeon™ processor

H = Mobile Intel ® Celeron ® processor at 466/433/400/366/333/300 and 266 MHz
J = 64-bit Intel® Xeon™ processor MP with 1MB L2 Cache
K = Mobile Intel ® Pentium ® III processor

L =

Intel ® Celeron ® D processor

M = Mobile Intel ® Celeron ® processor
N = Intel ® Pentium ® 4 processor

O = Intel ® Xeon™ processor MP

P = Intel ® Xeon™ processor

Q = Mobile Intel

Pentium

4 processor supporting Hyper-Threading Technology on 90-

nm process technology

R = Intel® Pentium® 4 processor on 90 nm process

S = 64-bit Intel® Xeon™ processor with 800 MHz system bus (1 MB and 2 MB L2

cache versions)

T = Mobile Intel® Pentium® 4 processor-M

V = Mobile Intel® Celeron® processor on .13 Micron Process in Micro-FCPGA

Package

W= Intel® Celeron® M processor

X = Intel

Pentium

M processor on 90nm process with 2-MB L2 Cache

Y = Intel® Pentium® M processor

Z = Mobile Intel ® Pentium ® 4 processor with 533 MHz system bus

AA = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor on
65nm

AB = Intel

Pentium

4 processor on 65 nm process

AC = Intel

Celeron

processor in 478 Pin Package

AD = Intel

Celeron

D processor on 65nm process

AE = Intel

Core

Duo Processor and Intel

Core

Solo processor on 65nm process

AF = Dual-Core Intel® Xeon® processor LV
AG = Dual-Core Intel® Xeon® Processor 5100 Series

AH = Intel® Core™2 Duo mobile processor

AI = Intel® Core™2 Extreme Processor X6800

and Intel® Core™2 Duo Desktop

Processor E6000

Sequence

AL = Dual-Core Intel® Xeon® Processor 7100 Series

NO. E0 nC1 nD1 Plans

ERRATA

AC1 X X X NoFix

I/O restart in SMM may fail after simultaneous machine check
exception (MCE)

AC2 X X X NoFix

MCA registers may contain invalid information if RESET#
occurs and PWRGOOD is not held asserted

Summary of Contents for Celeron Series

Page 1: ...R Notice The Intel Celeron Processor in the 478 Pin Package may contain design defects or errors known as errata which may cause the product to deviate from published specifications Current characteri...

Page 2: ...marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel Cel...

Page 3: ...ge Specification Update 3 Contents Revision History 4 Preface 6 Summary Tables of Changes 8 General Information 14 Component Identification Information 15 Errata 19 Specification Changes 46 Specificat...

Page 4: ...Updated processor identification information table March 2003 010 Added Specification clarification AC1 Updated processor identification information table Added Errata AC44 and AC45 May 2003 011 Upda...

Page 5: ...ble of changes Updated Microcode Update Guide and PDB file guide Added Erratum AC66 October 2005 026 Updated erratum AC40 January 2006 027 Updated document numbers for Software Developers Manuals Marc...

Page 6: ...d Documents Document Title Document Number Intel Celeron Processor in the 478 Pin Package up to 1 80 GHz Datasheet http developer intel com design celeron datashts 251748 htm Intel Celeron Processor o...

Page 7: ...ed specifications Hardware and software designed to be used with any given stepping must assume that all errata documented for that stepping are present on all devices Specification Changes are modifi...

Page 8: ...s the following notations Codes Used in Summary Table Stepping X Erratum Specification Change or Clarification that applies to this stepping No mark or Blank Box This erratum is fixed in listed steppi...

Page 9: ...process S 64 bit Intel Xeon processor with 800 MHz system bus 1 MB and 2 MB L2 cache versions T Mobile Intel Pentium 4 processor M V Mobile Intel Celeron processor on 13 Micron Process in Micro FCPGA...

Page 10: ...X NoFix The IA32_MC1_STATUS register may contain incorrect information for correctable errors AC15 X X X NoFix Debug mechanisms may not function as expected AC16 X X X NoFix Machine check architectur...

Page 11: ...Processor Does not Flag GP on Non zero Write to Certain MSRs AC36 X Fixed L2 cache may contain stale data in the Exclusive state AC37 X X X NoFix Simultaneous assertion of A20M and INIT may result in...

Page 12: ...y Slow Memory Could Lead to a System Hang AC59 X X X No Fix Machine Check Exceptions May not Update Last Exception Record MSRs LERs AC60 X X No Fix Stores to Page Tables May Not Be Visible to Pagewalk...

Page 13: ...ns ERRATA AC69 X X X NoFix Debug Status Register DR6 Breakpoint Condition Detected Flags May be set Incorrectly NO E0 nC1 nD1 SPECIFICATION CHANGES No update for this Month NO E0 nC1 nD1 SPECIFICATION...

Page 14: ...ssor in the 478 pn package Figure 1 Example Markings for the Intel Celeron Processor on 0 13 Micron Process and or in the 478 Pin Package 2A GHZ 512 400 1 50V SYYYY XXXXXX FFFFFFFF NNNN i m 01 Frequen...

Page 15: ...nstruction is executed with a 1 in the EAX register and the model field of the Device ID register accessible through Boundary Scan 3 The Brand ID corresponds to bits 7 0 of the EBX register after the...

Page 16: ...7h 2 10 GHz 400 MHz FC PGA2 31 0 mm rev 1 0 2 5 SL6RS C1 128K 0F27h 2 10 GHz 400 MHz FC PGA2 31 0 mm rev 1 0 5 8 10 SL6VS D1 128K 0F29h 2 10 GHz 400 MHz FC PGA2 31 0 mm rev 1 0 5 8 9 SL6SY C1 128K 0F2...

Page 17: ...8K 0F29h 2 30 GHz 400 MHz FC PGA2 31 0 mm rev 1 0 2 6 8 SL6T2 C1 128K 0F27h 2 30 GHz 400 MHz FC PGA2 31 0 mm rev 1 0 2 6 SL6T5 C1 128K 0F27h 2 30 GHz 400 MHz FC PGA2 31 0 mm rev 1 0 2 6 8 SL6VU C1 128...

Page 18: ...Hz FC PGA2 31 0 mm rev 1 0 8 9 SL77V D1 128K 0F29h 2 80 GHz 400 MHz FC PGA2 31 0 mm rev 1 0 2 8 SL7EZ D1 128K 0F29h 1 60GHz 400MHz 31 0 mm FC Rev 1 0 2 8 SL7RU D1 128K 0F29h 1 80GHz 400MHz 31 0 mm FC...

Page 19: ...e restart and shutdown of the processor Workaround If a system implementation must support both SMM and board I O restart the first thing the SMM handler code should do is check for a pending MCE If t...

Page 20: ...action Is Not Retried after BINIT Problem If the first transaction of a locked sequence receives a HITM and DEFER during the snoop phase it should be retried and the locked sequence restarted However...

Page 21: ...Instruction Problem If a data page fault PF and alignment check fault AC both occur for an unlocked CMPXCHG8B instruction then PF will be flagged Implication Software that depends AC before PF will b...

Page 22: ...e counter are not written at the same time as the lower 32 bits the increment due to the non zero event counter may cause a carry to the upper bits such that the performance counter contains a value a...

Page 23: ...ten by a different mechanism than the rest of the register For uncorrectable errors the other fields in the IA32_MC0_STATUS register are only updated by the first error Any subsequent errors cause the...

Page 24: ...register matches and any one of those debug registers is enabled in DR7 all of the matches should be reported in DR6 when the processor goes to the debug handler This is not true during a REP instruc...

Page 25: ...hould be logged in the IA32_MC2_STATUS register but no machine check exception should be generated Uncorrectable loads on bank 2 which would normally be logged in the IA32_MC2_STATUS register are not...

Page 26: ...tion sequence CAUTION The processor s Thermal Monitor feature may not function if the timeout counter is not re enabled after completing the PCI initialization After the system is fully initialized th...

Page 27: ...FDP may become corrupted Workaround This erratum will not occur with floating point exceptions masked If floating point exceptions are unmasked then performance counting of x87 loads should be disable...

Page 28: ...write combines to the same address there is a small window where the L0 is corrupt and loads can retire with this corrupted data This erratum occurs in the following scenario A Read For Ownership RFO...

Page 29: ...les located in write combining memory may return incorrect data Intel has not been able to reproduce this erratum with commercially available software Workaround Do not place page directories and or p...

Page 30: ...2 Cache Line and ECC Error Combination May Result in Loss of Cache Coherency Problem When a Read for Ownership RFO cycle has a 64 bit address match with an outstanding read hit on a line in the L2 cac...

Page 31: ...program the at retirement event Counting is enabled via counter configuration control registers CCCR while the event count is read from one of the associated counters When counting logic is configure...

Page 32: ...L transaction to the same cache line address as an outstanding BRL or BRIL As it is not typical behavior for a single processor to have a BWL and a BRL BRIL concurrently outstanding to the same addres...

Page 33: ...fore the WC Buffers write modified data back filling the L2 with stale data 7 The writeback from the WC Buffers completes leaving stale data for cacheline A in the Exclusive E state in the L2 cache Im...

Page 34: ...the processor is not affected Workaround None identified Status For the steppings affected see the Summary Tables of Changes AC40 A Write to an APIC Register Sometimes May Appear to Have Not Occurred...

Page 35: ...ossible that the processor may hang while trying to evict the line Implication If this erratum occurs it may result in a system hang Intel has not observed this erratum with any commercially available...

Page 36: ...failure will be reported in the EAX register bit 0 however this failure can be ignored since it is not accurate Workaround It is possible for BIOS to workaround this issue by masking off bit 0 in the...

Page 37: ...8 byte load lock onto the system bus A subsequent 8 byte store unlock is expected but instead a 4 byte store unlock occurs Correct data is provided since only the lower bytes change however external...

Page 38: ...types does not introduce any functional failures such as system hangs or memory corruption Workaround None identified Status For the steppings affected see the Summary Tables of Changes AC51 A 16 bit...

Page 39: ...ad in the microcode routine will trigger the data breakpoint resulting in a Debug Exception Implication An incorrect Debug Exception DB may occur if data breakpoint is placed on an FP instruction Inte...

Page 40: ...RFO retries Implication This erratum has not been observed in any commercially available operating system or application The aliasing of memory regions a condition necessary for this erratum to occur...

Page 41: ...nd the younger memory access Refer to the IA 32 Intel Architecture Software Developer s Manual for the correct way to update page tables Software that conforms to the Software Developer s Manual will...

Page 42: ...e A BTS PEBS record can be written that will wrap at the 4G boundary IA32 or 2 64 boundary EMT64 mode and write memory outside of the BTS PEBS buffer Implication Software that uses BTS PEBS near the 4...

Page 43: ...o the user Any higher priority architectural event that arrives and is handled while the interim paging event is occurring may see the modified value of CR2 Implication The value in CR2 is correct at...

Page 44: ...ared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Problem Software which is written so that multiple agents can modify the same sha...

Page 45: ...ebug register access MOV DRx r32 or MOV r32 DRx results in a general detect exception condition Implication Due to this erratum the breakpoint condition detected flags may be set incorrectly Workaroun...

Page 46: ...in this section apply to the following documents Intel Celeron Processor in the 478 Pin Package Datasheet Intel 64 and IA 32 Intel Architectures Software Developer s Manual Volumes 1 2 A 2 B 3 A and...

Page 47: ...d identify the relative time occurrence of processor events The counter s architecture includes the following components TSC flag A feature bit that indicates the availability of the time stamp counte...

Page 48: ...The TSD flag allows use of this instruction to be restricted to programs and procedures running at privilege level 0 A secure operating system would set the TSD flag during system initialization to d...

Page 49: ...on a per logical processor basis See Section 10 8 for detail on processor capabilities The first two methods use performance counters and can be set up to cause an interrupt upon overflow for samplin...

Page 50: ...loper s Manual Volumes 1 2 A 2 B 3 A and 3 B All Documentation Changes will be incorporated into a future version of the appropriate Celeron processor documentation Note Documentation changes for IA 3...

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