Errata
R
26
Intel
®
Celeron
®
Processor in the 478-Pin Package Specification Update
AC17.
Processor May Timeout Waiting for a Device to Respond after 0.67
Seconds
Problem:
The PCI 2.1 target initial latency specification allows two seconds for a device to respond during
initialization-time. The processor may timeout after only approximately 0.67 seconds. When the
processor times out it will hang with IERR# asserted. PCI devices that take longer than 0.67
seconds to initialize may not be initialized properly.
Implication:
System may hang with IERR# asserted.
Workaround:
Due to the long initialization time observed on some commercially available PCI cards, it may be
necessary to disable the timeout counter during the PCI initialization sequence. This can be
accomplished by temporarily setting Bit 5 of the MISC_ENABLES_MSR located at address
1A0H to 1. This model specific register (MSR) is software visible but should only be set for the
duration of the PCI initialization sequence. It is necessary to re-enable the timeout counter by
clearing this bit after completing the PCI initialization sequence. CAUTION: The processor's
Thermal Monitor feature may not function if the timeout counter is not re-enabled after
completing the PCI initialization.
After the system is fully initialized, this erratum may occur either when a PCI device is hot added
into the system or when a PCI device is transitioned from D3 cold. System software responsible
for completing the hot add and the power state transition from D3 cold should allow for a delay of
the target initial latency prior to initiating configuration accesses to the PCI device.
Status:
For the steppings affected, see the
Summary Tables of Changes.
AC18.
Cascading of Performance Counters Does Not Work Correctly When
Forced Overflow Is Enabled
Problem:
The performance counters are organized into pairs. When the CASCADE bit of the Counter
Configuration Control Register (CCCR) is set, a counter that overflows will continue to count in
the other counter of the pair. The FORCE_OVF bit forces the counters to overflow on every non-
zero increment. When the FORCE_OVF bit is set, the counter overflow bit will be set but the
counter no longer cascades.
Implication:
The performance counters do not cascade when the FORCE_OVF bit is set.
Workaround:
None identified.
Status:
For the steppings affected, see the
Summary Tables of Changes.
