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1000BASE-T/100BASE-TX/10BASE-T Physical Layer Compliance Tests Manual

Intel Confidential

141

100Base-TX Test Procedure for the 82544 Chip

I.4.4

Test Fixtures

100 Ohm UTP Test Load. Fixture: F9.1.2.A.

I.4.5

Test Procedure

1. Connect the test equipment and Unit Under Test (UUT), as shown in

.

2. Use software or firmware control to force the unit under test to transmit frames in 100BASE-

TX mode.

3. Configure the oscilloscope according to

.

Table I-3. For Positive Peak Differential Output Amplitude

Table I-4. For Negative Peak Differential Output Amplitude

I.4.6

Notes for Using Pulse-Width Triggering

Note:

Most of the following procedure is very similar to the procedure for 9.1.2.1 Differential Output
Voltage (

) except: (1) the horizontal scale is only 1 nsec per division, and (2) the

operator is required to scroll left and right through the pulse -- to see if the MLT mid-level
shoulders are at least 20 nsec wide on both sides of the pulse; AND for rise and fall times, the
operator must make several different plots with both horizontal cursors and “cross-hair” cursors.

1. Set the trigger level to ~500 mV.

2. Select Pulse-Width triggering.

3. Start with the upper bound at ~118 nsec, and the lower bound at ~106 nsec.

4. Set the Trigger Mode to NORMAL.

Scope Parameter

Setting

Horizontal Scale

1 ns/division

Vertical Range

-100 mV to +1100 mV (1200 mV over the full vertical scale)

Vertical Position

-3.5 divisions to -4.0 divisions

Trigger Type

Positive, Pulse Width Triggering:
~116 ns lower bound, ~124 ns upper bound
(If shorter pulses are used, the lower bound may be lowered.)

Trigger Level

+500 mV

Trigger Signal

Differential signal at the pins of the test load.

Scope Parameter

Setting

Horizontal Scale

1 ns/division

Vertical Range

-1100 mV to +100 mV (1200 mV over the full vertical scale)

Vertical Position

+3.5 divisions to +4.0 divisions

Trigger Type

Negative, Pulse Width Triggering:
~116 ns lower bound, ~124 ns upper bound
(If shorter pulses are used, the lower bound may be lowered.)

Trigger Level

-500 mV

Trigger Signal

Differential signal at the pins of the test load.

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Summary of Contents for 1000BASE-T

Page 1: ...1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual for Gigabit Ethernet Products Networking Silicon Intel Confidential Revision 3 8 November 2003 ...

Page 2: ... not rely on the absence or characteristics of any features or instructions marked reserved or undefined Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them The Intel product s described herein may contain design defects or errors known as errata which may cause the product to deviate from pub...

Page 3: ...E Gigabit Ethernet testing 2 0 Aug 2002 General edits and additional information included in Appendix C 1 2 Dec 2001 Listed required versus recommended tests in Sections 1 1 1 and 1 1 2 Added new section for alien crosstalk noise rejection test Included diagrams for test fixtures in Appendix A Changed Appendix C from Calculations for Worst Case Gigabit Cable to Worst Case Cable for Gigabit Jitter ...

Page 4: ...1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual iv Intel Confidential Note This page is intentionally left blank ...

Page 5: ... Purpose 9 2 2 Specification 9 2 3 Test Equipment 10 2 4 Test Fixtures 10 2 5 Test Procedure 10 3 1000BASE T Maximum Output Droop 15 3 1 Test Purpose 15 3 2 Specification 15 3 3 Test Equipment 16 3 4 Test Fixtures 16 3 5 Test Procedure 16 4 1000BASE T Receiver Differential Input Signals Bit Error Rate 19 4 1 Test Purpose 19 4 2 Specification 19 4 3 Test Equipment 19 4 4 Test Fixtures 19 4 5 Test P...

Page 6: ...n 35 9 3 Test Equipment 36 9 4 Test Fixtures 36 9 5 Test Procedure 36 10 100Base TX Signal Amplitude Symmetry 39 10 1 Test Purpose 39 10 2 Specification 39 10 3 Test Procedure 39 11 100Base TX Transmitter Return Loss 41 11 1 Test Purpose 41 11 2 Specification 41 11 3 Test Equipment 41 11 4 Test Fixtures 41 11 5 Test Procedure 41 12 100Base TX Rise and Fall Times 45 12 1 Test Purpose 45 12 2 Specif...

Page 7: ...eak Differential Output Voltage on TD Circuit 67 17 1 Test Purpose 67 17 2 Specification 67 17 3 Test Equipment 67 17 4 Test Fixtures 67 17 5 Test Procedure 68 18 10Base T Harmonic Content 71 18 1 Test Purpose 71 18 2 Specification 71 18 3 Test Equipment 71 18 4 Test Fixtures 71 18 5 Test Procedure 71 19 10Base T TD Circuit Impedance Transmitter Return Loss 73 19 1 Test Purpose 73 19 2 Specificati...

Page 8: ...ures 93 24 5 Test Procedure 93 A 1000Base T Test Fixtures and Calibration Load Fixtures 97 A 1 Fixture 40 25 97 A 2 Fixture 40 6 1 1 1 A Differential Breakout Cable 98 A 3 Fixture 40 6 1 1 1 Test Cable 98 A 4 Fixture 40 8 3 1 A 100 A 5 Fixture 40 8 3 1 B 100 A 6 Fixture 40 8 3 1 C 101 A 7 Fixture 40 28A 101 A 8 Fixture 40 28B 102 A 9 Fixture 40 32 102 B Test Fixture Construction Tips and Informati...

Page 9: ...n Circuit Inductance ANSI specification 9 1 7 126 G 9 Duty Cycle Distortion ANSI specification 9 1 8 127 G 10 Transmit Jitter ANSI specification 9 1 9 128 G 11 Differential Input Signals ANSI specification 9 2 1 129 G 12 Receiver Common Mode Rejection ANSI specification 9 2 3 129 H Manual Register Settings 131 H 1 82540 and 82546 Families 131 H 2 82541 and 82547 Families 132 H 3 82544 Family 132 I...

Page 10: ...nce Tests Manual x Intel Confidential I 5 1 Test Case 148 I 5 2 Test Purpose 148 I 5 3 Specification 148 I 5 4 Test Equipment 148 I 5 5 Test Fixtures 148 I 5 6 Test Procedure 149 I 5 7 Generic Oscilloscope Settings 149 I 5 8 Duty Cycle Distortion Data 151 ...

Page 11: ...ts are included throughout the document in shaded boxes The test methods described in this document have been customized to test Intel networking silicon only Results may vary if these procedures are used on other manufacturers networking devices 1 1 Reference Documents IEEE Standard 802 3 2000 Supplement to Carrier Sense Multiple Access with Collision Detection CSMA CD Access Method and Physical ...

Page 12: ...rated in Figure 1 1 Figure 1 1 Ambiguous Trigger Level 1 2 2 2 Signal Does Not Appear If the signal does not appear or appears only for an instant the trigger level may be too high Reducing the trigger level should cause the signal to appear or re appear 1 2 3 Displaying Waveforms When observing waveforms on the scope display it is important to understand the purpose of the measurement being perfo...

Page 13: ...1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual Intel Confidential 3 Introduction Figure 1 2 Poor Resolution Wide View Figure 1 3 Good Resolution with Room for Improvement ...

Page 14: ...o appear unstable because each successive signal is not exactly the same as the previous one By averaging the waveforms together random noise will be filtered from the display and a more representative signal will appear Some measurements require the scope display to be set to Infinite Persistence In this case it is important that each successive waveform falls within specified boundary conditions...

Page 15: ...5 meter Category 5 cable with female pins on 0 1 inch centers at one end Length of Category 5 cable that conforms to the following For 1000BASE T section 40 7 of the IEEE 802 3 specification The parameters that have the greatest impact on cable length are insertion loss and propagation delay For 100BASE TX section 25 4 6 of the IEEE 802 3 specification For 10BASE T section 14 4 of the IEEE 802 3 s...

Page 16: ...lementation confidence These tests are not required but if completed will ensure a higher quality design 1000Base T PHY Conformance Tests Pre Test IEEE Compliance Test 40 6 1 2 1 Peak Differential Output Voltage and Level Accuracy X X 40 6 1 2 2 Maximum Output Droop X X 40 6 1 3 2 Receiver Differential Input Signals Receive Bit Error Rate X X 40 8 3 1 MDI Return Loss X 40 6 1 3 4 Alien Crosstalk N...

Page 17: ...D Circuit X X 10Base T Transmitter Output Timing Jitter without Cable Model X X 10Base T TD Circuit Impedance Transmitter Return Loss X 10Base T TD Circuit Common Mode Output Voltage X 10Base T Transmitter Output Timing Jitter with Cable Model X 10Base T RD Receiver Circuit Signal Acceptance Test BER X 10Base T RD Circuit Differential Input Impedance Receiver Return Loss X 10Base T Harmonic Conten...

Page 18: ...Introduction 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 8 Intel Confidential Note This page is intentionally left blank ...

Page 19: ...pose To measure the peak differential output voltage on all four channels and examine the linearity of each channel This test uses Test Mode 1 as defined by the IEEE 802 3 Specification section 40 6 1 1 2 An example of the test mode 1 waveform is shown below 2 2 Specification Points A B 0 67 to 0 82 Vpk Amplitude Symmetry 1 delta between A and B Points C D 0 5 A or B 2 The above is true for all fo...

Page 20: ... Level Accuracy 40 6 1 2 1 Test from the 1000BASE T PHY Configuration Tests menu in gigconf exe 4 Measure the output voltage with a differential probe connected across the 100 ohm test load for each channel 5 Adjust oscilloscope to the settings for Point A as shown in the following table and figure Differential Probe w 1 GHz BW Unit Under Test UUT Digitizing Oscilloscope Test Fixture 40 25 100 Ohm...

Page 21: ...t 6 Repeat Step 5 for Point B Table 2 2 Point B Peak Voltage Figure 2 3 Example Point B Measurement 7 Repeat 5 for Point C Trigger Settings Trigger Type Polarity Limits Level Pulse width Negative 5 6 ns to 8 6 ns 500 mV Scaling Vertical Scale Vertical Position Horizontal Scale 150 mV division 3 0 division 5 ns division Cursors Display Mode Acquisition Mode Horizontal bars Vectors Average on ...

Page 22: ...pe Polarity Limits Level Pulse width Positive 7 ns to 9 ns 251 mV Scaling Vertical Scale Vertical Position Horizontal Scale 75 mV division 3 0 division 5 ns division Cursors Display Mode Acquisition Mode Horizontal bars Vectors Average on Trigger Settings Trigger Type Polarity Limits Level Pulse width Negative 5 6 ns to 8 6 ns 278 mV Scaling Vertical Scale Vertical Position Horizontal Scale 75 mV ...

Page 23: ...Physical Layer Compliance Tests Manual Intel Confidential 13 1000BASE T Peak Differential Output Voltage and Level Accuracy Figure 2 5 Example Point D Measurement 9 Verify that the measurements meet specifications for all four points ...

Page 24: ...1000BASE T Peak Differential Output Voltage and Level Accuracy 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 14 Intel Confidential Note This page is intentionally left blank ...

Page 25: ...waveform is shown below 3 2 Specification Point G amplitude 73 1 of point F amplitude point G is exactly 500 ns after F Point J amplitude 73 1 of point H amplitude point J is exactly 500 ns after H The above is true for all four MDI channels If the LAN design does not meet the output droop requirement the open circuit inductance OCL for all four channels of the magnetics module should be verified ...

Page 26: ...from the 1000BASE T PHY Configuration Tests menu in gigconf exe 4 Adjust the oscilloscope to the settings for Points F and G 5 Measure the output voltage with a differential probe connected across the 100 ohm test load for each channel Differential Probe w 1 GHz BW Unit Under Test UUT Digitizing Oscilloscope Test Fixture 40 25 100 Ohm Resistive Load RX RJ 45 TX Point F and G Pulse Droop Trigger Se...

Page 27: ... below Point H peak 1 020 Volts Figure 3 2 Example Maximum Output Droop Measurement Point H Point H and J Pulse Droop Trigger Settings Trigger Type Polarity Limits Level Pulse width Positive 7 ns to 9 ns 500 mV Scaling Vertical Scale Vertical Position Horizontal Scale 150 mV division 3 0 division 200 ns division Cursors Display Mode Acquisition Mode Horizontal bars for H Crosshairs for H and J Vec...

Page 28: ... 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 18 Intel Confidential Point J 500 ns after H 0 984 Volts Figure 3 3 Example Maximum Output Droop Measurement Point J 9 Verify the measurements meet specifications ...

Page 29: ...cturing lot See Appendix E for details on constructing LAN cables 4 2 Specification The receiver shall have a frame error rate of less than 10 7 for 125 octet frames A frame error rate of 10 7 for 125 octet frames is equivalent to a bit error rate BER of 10 10 for any size of frame 4 3 Test Equipment UUT with gigconf exe software Second PC running gigconf exe with either a 1000BASE T network inter...

Page 30: ...good frames received _Receive_Good_Packets BF number of bytes frame BB 8 number of bits byte Note Conditions where the transmit link partner overwhelms the receive unit should be avoided When this happens the receive statistics counters may show RX No Resources RX No Buffers or a large number of missed packets This complicates the BER calculation and the equations for the calculations will not yie...

Page 31: ...s using a worst case max insertion loss and propagation delay test cable as defined in the IEEE 802 3 specification section 40 7 5 3 Test Equipment UUT with gigconf exe software Second PC with Ethernet network interface card NIC that can be forced to transmit 100BASE TX scrambled idle signals Third PC with gigconf exe software with either a 1000BASE T NIC or LAN on Motherboard LOM for a link partn...

Page 32: ...f the UUT 8 Repeat steps 5 to 7 for each remaining channel Four sets of receive BER data should exist when the test is completed 9 Verify the measurements meet specifications Note Before injecting the differential 100BASE TX scrambled idles a baseline receive BER test should be performed Without the injected noise signal the receive BER should equal 0 zero Unit Under Test UUT RJ 45 1000Base T Tran...

Page 33: ...o 40 MHz and 10 20LOG f 80 dB from 40 MHz to 100 MHz where f is in MHz 6 3 Test Equipment Vector network analyzer BNC cable with 50 ohm characteristic impedance UUT with gigconf exe test software 6 4 Test Fixtures Fixture 40 8 3 1 A Balun test fixture Appendix A Fixture 40 8 3 1 B calibration standards Appendix A Fixture 40 8 3 1 C square pin fixture Appendix A 6 5 Test Procedure 1 Connect the equ...

Page 34: ...ircuit standard and the 100 ohm calibration load After calibration is completed ensure that correction is turned on Note once the S11 calibration has been completed care should be taken to not move the test setup more than necessary Changes in the layout of the test setup can change the electrical characteristics of the setup and lead to erroneous results UUT RJ 45 Fixture 40 8 3 1 A Network Analy...

Page 35: ...nterface s return loss on channel A 7 Repeat the calibration and measurement process for the remaining three channels Calculating Theoretical Return Loss To solve for theoretical return loss given known impedances Ztransmitter Balanced output impedance of the balun for example 100 Ω Zload The impedance of any load connected to the output of the balun RL_in_dB For any load on the 100 Ω output of th...

Page 36: ...or each channel An example graph is shown below Figure 6 1 Example Measurement Note Not all return loss measurements will look exactly like the example above The most important part of the return loss measurement is to ensure that every point on the return loss line is below the limit specified by the IEEE 802 3 specification 8 Verify the measurements meet specifications ...

Page 37: ... 32 the common mode output voltage Ecm_out on any transmit pair shall be less than 50 mV peak to peak 7 3 Test Equipment Digitizing oscilloscope with 1 GHz or greater bandwidth Differential probes with 1 GHz or greater bandwidth 7 4 Test Fixtures Test Fixture 40 32 Appendix A 7 5 Test Procedure 1 Connect the test equipment as shown in the figure below Note it is important to pay close attention to...

Page 38: ...t scope settings for negative common mode measurement Differential Probe w 1 GHz BW Unit Under Test UUT Digitizing Oscilloscope Test Fixture 40 32 100 Ohm Resistive Load RX RJ 45 TX To Chassis GND can be metal shield on RJ 45 Scope Parameter Setting Horizontal Scale 2 ns division Vertical Range 25 mV to 25 mV at 10 vertical divisions this equals 5 mV division Trigger Type Level and positive or neg...

Page 39: ...e cursor on the maximum or peak voltage 9 Record maximum or peak amplitude value s If data is being plotted there should be at least two graphs for each channel positive peak and negative peak Figure 7 1 Common Mode Output Voltage Negative Peak Figure 7 2 Common Mode Output Voltage Positive Peak 10 Verify the measurements meet specifications MDI Channel Ecm Output mV pk pk A 14 70 B 14 30 C 16 90 ...

Page 40: ...1000BASE T MDI Common Mode Output 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 30 Intel Confidential Note This page is intentionally left blank ...

Page 41: ...connector also known as the Active Output Interface or AOI 8 2 Specification For UTP the differential output voltage VOUT as defined in specification 9 1 3 and Figure 8 1 shall be 950 mV VOUT 1050 mV 1 Figure 8 1 Waveform at Active Output Interface2 8 3 Test Equipment Oscilloscope with at least 1 GHz bandwidth Differential probe with at least 1 GHz bandwidth and capacitance less than or equal to 1...

Page 42: ...re 40 25 100 Ohm Resistive Load RX RJ 45 TX Table 8 1 Setting for Positive Differential Output Voltage UTP Scope Parameter Setting Horizontal Scale 25 ns division Vertical Range 150 mV to 1050 mV 1200 mV over the full vertical scale Trigger Type Positive pulse width triggering 116 ns lower bound 128 ns upper bound Trigger Level 500 mV Record Length Large enough to enable viewing of one complete ML...

Page 43: ... Parameter Setting Pulse Width Triggering Triggering information is provided to give a good starting point for measurement The following guidelines will help the tester achieve the most stable display 1 Set the trigger level to approximately 500 mV 2 Select pulse width triggering 3 Set the upper bound parameter to approximately 200 ns and the lower bound parameter to approximately 116 ns 4 Set the...

Page 44: ...Manual 34 Intel Confidential Figure 8 3 and Figure 8 4 provide examples of data for the differential output voltage measurement Figure 8 3 Positive Peak Differential Output Voltage Vpeak 1 014 V Figure 8 4 Negative Peak Differential Output Voltage Vpeak 1 011 V 8 Verify the measurements meet specifications ...

Page 45: ... performing a straight line best fit to an output waveform consisting of 14 bit times of no transition preceded by a transition from zero to either plus or minus VOUT as shown in Figure 9 1 VOUT is defined to be the intersection of the straight line best fit for amplitude with the vertical line indicating the start of the transition from 0 V to VOUT The differential signal overshoot shall not exce...

Page 46: ...X PHY Configuration Tests menu in gigconf exe select the Amplitude Symmetry 9 1 2 2 test 3 Configure the oscilloscope according to Table 9 1 Differential Probe w 1 GHz BW Unit Under Test UUT Digitizing Oscilloscope Test Fixture 40 25 100 Ohm Resistive Load RX RJ 45 TX Table 9 1 Setting for Positive Waveform Overshoot Scope Parameter Setting Horizontal Scale 25 ns division Vertical Range 150 mV to ...

Page 47: ...Waveform Overshoot Scope Parameter Setting Horizontal Scale 25 ns division Vertical Range 1125 mV to 75 mV 1200 mV over the full vertical scale Trigger Type Negative pulse width triggering 116 ns lower bound 128 ns upper bound Trigger Level 500 mV Record Length Large enough to enable viewing of one complete MLT 3 3 level waveform by scrolling horizontally Display Type Average Pulse Width Triggerin...

Page 48: ...tage 6 Record the results 7 Select the paired dot cursors Move one cursor to the zero voltage crossing and the other cursor to 8 ns beyond the first cursor position The overshoot voltage shall have decayed to within 1 of the steady state voltage within 8 ns following the beginning of the differential signal transition 8 Repeat steps 3 through 7 using Table 9 2 to measure negative overshoot Figure ...

Page 49: ... the VOUT magnitude to VOUT magnitude shall be between the limits 1 10 3 Test Procedure 1 Perform test described in Section 9 if it has not already been done 2 Calculate the ratio of VOUT to VOUT using the values from the results of Section 9 3 Record the results 4 Verify the measurements meet specifications Figure 10 1 Calculating the Ratio of VOUT to VOUT 1 ANSI X3 263 1995 p 29 0 98 VOUT V OUT ...

Page 50: ...100Base TX Signal Amplitude Symmetry 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 40 Intel Confidential Note This page is intentionally left blank ...

Page 51: ...an 10 dB from 60 MHz to 80 MHz The impedance environment for the measurement of the UTP AOI return loss shall be 100 15 Ω The impedance environment shall be nominally resistive with a magnitude of phase angle less than 3 over the specified measurement frequency range 1 11 3 Test Equipment Network analyzer 50 KHz to 500 MHz range S parameter test set or transmission reflection test set Host compute...

Page 52: ...nnect the test fixture but keep it close to the UUT 7 Perform a 1 port full calibration with an open short and 100 Ω load by connecting the calibration fixture to the RJ 45 connection in place of the UUT UUT RJ 45 Network Spectrum Analyzer Cat 5 Cable 50 Ohm BNC RJ 45 50 Ohms 100 Ohms Transmission Reflection Test Set 50 Ohm Termination on unused balun 100 Ohms 50 Ohms Table 11 1 Network Analyzer S...

Page 53: ... 2 Figure 11 2 Transmitter Return Loss 10 Set the marker to the worst case return loss between 2 MHz and 30 MHz Record the amplitude dB of return loss 11 Repeat step 10 from 30 MHz to 60 MHz and from 60 MHz to 80 MHz 12 Verify the measurements meet specifications Calculating Theoretical Return Loss To solve for theoretical return loss given known impedances Ztransmitter Balanced output impedance o...

Page 54: ...100Base TX Transmitter Return Loss 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 44 Intel Confidential Note This page is intentionally left blank ...

Page 55: ...ltage nominally zero to either VOUT or VOUT Signal fall is conversely defined as a transition from the VOUT or VOUT to the baseline voltage The rise and fall times of the waveform shall be determined as the time difference between the 10 and the 90 voltage levels of the signal transition where 100 is represented by VOUT in Figure 12 1 Measured rise and fall times shall be between the limits 3 0 ns...

Page 56: ...Configuration Tests menu in gigconf exe select the Rise Fall Times 9 1 6 test 3 Configure the oscilloscope according to Table 12 1 Differential Probe w 1 GHz BW Unit Under Test UUT Digitizing Oscilloscope Test Fixture 40 25 100 Ohm Resistive Load RX RJ 45 TX Table 12 1 Setting for Positive Rise and Fall Times Scope Parameter Setting Horizontal Scale 1 ns division or 0 5 ns division Vertical Range ...

Page 57: ...ference between the maximum and minimum of all measured rise and fall times is less than or equal to 0 5 ns 11 Verify the measurements meet specifications Table 12 2 Setting for Negative Rise and Fall Times Scope Parameter Setting Horizontal Scale 1 ns division or 0 5 ns division Vertical Range 1125 mV to 75 mV 1200 mV over the full vertical scale Trigger Type Negative pulse width triggering 116 n...

Page 58: ...sical Layer Compliance Tests Manual 48 Intel Confidential Figure 12 3 Positive Rise Time Measurement Note The rise time t in Figure 12 3 is measured to be 3 68 ns Figure 12 4 Positive Fall Time Measurement Note The fall time t in Figure 12 4 is measured to be 3 63 ns ...

Page 59: ...nual Intel Confidential 49 100Base TX Rise and Fall Times Figure 12 5 Negative Rise Time Measurement Note The rise time t in Figure 12 5 is measured to be 3 68 ns Figure 12 6 Negative Fall Time Measurement Note The fall time t in Figure 12 6 is measured to be 3 83 ns ...

Page 60: ...100Base TX Rise and Fall Times 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 50 Intel Confidential Note This page is intentionally left blank ...

Page 61: ...al output waveform The 50 times at the four successive MLT 3 transitions generated by a 01010101 NRZ non return to zero bit sequence shall be used The deviations of the 50 crossing times from a best fit to a time grid of 16 ns spacing shall not exceed 0 25 ns as shown in Figure 13 1 1 Figure 13 1 Active Output Interface Duty Cycle Distortion2 13 3 Test Equipment Oscilloscope with at least 1 GHz ba...

Page 62: ...select the Duty Cycle Distortion 9 1 8 test 3 Configure the oscilloscope according to the following table Differential Probe w 1 GHz BW Unit Under Test UUT Digitizing Oscilloscope Test Fixture 40 25 100 Ohm Resistive Load RX RJ 45 TX Table 13 1 Setting for Duty Cycle Distortion DCD Scope Parameter Setting Horizontal Scale 5 ns division Vertical Range 1200 mV to 1200 mV 2400 mV over the full vertic...

Page 63: ...s Pulse Width 16 50 ns 9 Record the results 10 Repeat steps 4 through 9 for the mid level negative waveform as shown in Figure 13 5 and Figure 13 6 11 Verify the measurements meet specifications Pulse Width Triggering Triggering information is provided to give a good starting point for measurement The following guidelines will help the tester achieve the most stable display 1 Set the trigger level...

Page 64: ...e TX Duty Cycle Distortion DCD 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 54 Intel Confidential Figure 13 4 Positive Pulse Width at 50 Figure 13 5 MLT 3 mid level width at 50 levels ...

Page 65: ...1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual Intel Confidential 55 100Base TX Duty Cycle Distortion DCD Figure 13 6 Negative pulse width at 50 amplitude level ...

Page 66: ...100Base TX Duty Cycle Distortion DCD 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 56 Intel Confidential Note This page is intentionally left blank ...

Page 67: ...luding contributions from duty cycle distortion and Baseline Wander shall not exceed 1 4 ns peak to peak 1 14 3 Test Equipment Oscilloscope with at least 1 GHz bandwidth Differential probe with at least 1 GHz bandwidth and capacitance less than or equal to 1 pF Host computer running gigconf exe 14 4 Test Fixtures 100 Ω UTP test load Appendix A 1 14 5 Test Procedure 1 Connect the test equipment and...

Page 68: ...tter Data Note The jitter of the waveform in figure 14 2 is measured at 920ps 5 Allow data to accumulate for one to ten minutes 6 Use the scope s vertical bar cursors to measure the widest X as shown in Figure 14 2 7 Record the results 8 Confirm that the resulting jitter is less than 1 4 ns 9 Verify the measurements meet specifications Table 14 1 Setting for Transmit Jitter Scope Parameter Setting...

Page 69: ...ing receive bit error rate tests with specification compliant Category 5 cables across a range of lengths from approximately 1 meter to greater than 100 meters maximum specification Insertion loss measurements and propagation delay measurements have shown high quality Category 5 cable ranging from 115 m to 130 m may be equal to a maximum specification cable depending on the vendor and the cable ma...

Page 70: ...he bit error rate BER 7 Repeat steps 1 through 7 for each cable length 8 Verify the measurements meet specifications 15 6 Calculating Bit Error Rate BER The basic BER equation is as follows where TGP number of good frames transmitted _Transmit_Good_Packets MP number of missed packets _Missed_Packets RGP number of good frames received _Receive_Good_Packets BF number of bytes frame BB 8 number of bi...

Page 71: ...rential Input Signals BER BER 1 200 000 0 1 199 995 1 200 000 1 024 8 5 09 x 10 10 This example passes because the resulting BER is less than 1 x 10 8 which is the maximum specification It is recommended that the test operator to obtain and read a copy of the gigconf exe PHY Conformance BER Test User s Guide ...

Page 72: ...100Base TX Differential Input Signals BER 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 62 Intel Confidential Note This page is intentionally left blank ...

Page 73: ...n 16 20log f 30 MHz dB from 30 MHz to 60 MHz where f frequency Greater than 10 dB from 60 MHz to 80 MHz 1 The impedance environment for the measurement of the UTP AII Active Input Interface return loss shall be 100 Ω 15 Ω The impedance environment shall be nominally resistive with a magnitude of phase angle less than 3 over the specified measurement frequency range 16 3 Test Equipment Network anal...

Page 74: ...4 dB Also verify that the open and short loads produce the expected results 8 From the 100 BASE TX PHY Configuration Tests menu in gigconf exe select the RX Return Loss 9 2 2 test 9 Reconnect the test fixture to the UUT The resulting network analyzer display should be similar to Figure 16 2 UUT RJ 45 Network Spectrum Analyzer Cat 5 Cable 50 Ohm BNC Cable RJ 45 50 Ohms 100 Ohms Transmission Reflect...

Page 75: ...100Base TX Receiver Return Loss Figure 16 2 Receiver Return Loss Data 10 Set the marker to the worst case return loss between 2 MHz and 30 MHz Record the amplitude dB of return loss 11 Repeat step 11 from 30 MHz to 60 MHz and from 60 MHz to 80 MHz 12 Verify the measurements meet specifications ...

Page 76: ...100Base TX Receiver Return Loss 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 66 Intel Confidential Note This page is intentionally left blank ...

Page 77: ...e To verify the TD circuit peak differential output voltage 17 2 Specification The peak differential output voltage on the TD circuit when terminated with a 100 ohm resistive load shall be between 2 2 V pk and 2 8 V pk for all data sequences 17 3 Test Equipment Digitizing Oscilloscope 100 MHz or greater bandwidth Differential Probes 100 MHz or greater Bandwidth Host computer running gigconf exe 17...

Page 78: ...Scale 10 to 50 ms division Vertical Scale 3 1 V to 3 1 V at 10 vertical divisions use 620 mV division at 8 divisions use 775 mV division Trigger Type Pulse width 148 ns lower bound 364 ns upper bound Trigger Level Typically 0 5 V to 1 7 V Pulse Width Triggering Triggering information is provided to give a good starting point for measurement The following guidelines will help the tester achieve the...

Page 79: ...al or from a 10 MHz signal to a 5 MHz signal Figure 17 2 Example 5MHz Measurement 5 Record the values 6 From the 10 BASE T PHY Configuration Tests menu in gigconf exe select the Amplitude 10MHz 1411 10 02 test 7 Repeat step 3 8 Locate the 10MHz signals after a stable trigger is obtained and measure positive and negative peak voltages See Figure 17 3 Locate regions of three periods for each signal ...

Page 80: ...10Base T Peak Differential Output Voltage on TD Circuit 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 70 Intel Confidential Figure 17 3 Example 10MHz Measurement 10 MHz VOUT ...

Page 81: ... Test Equipment Spectrum Analyzer CAT 5 twisted pair cable under 2 inches in length BNC cable with 50 ohm characteristic impedance 18 4 Test Fixtures Balun Test Fixture with 200 MHz or greater bandwidth Appendix D 5 18 5 Test Procedure 1 Insert CAT 5 cable into transmitter side of Balun fixture and connect Balun to Spectrum Analyzer or Network Analyzer through a BNC cable as shown in Figure 18 1 F...

Page 82: ... be attenuated if it is out of range on the spectrum analyzer 5 Record dBm at 10 MHz and dBm at highest amplitude harmonic The difference between the two markers must be greater than 27 dBm to ensure compliance with IEEE standards and specifications 6 Verify the measurements meet specifications Table 18 1 Analyzer Configuration for Harmonic Content Scope Parameter Settings Start Frequency 6 Mhz St...

Page 83: ...k Analyzer CAT 5 twisted pair cable under 2 inches in length BNC cable with 50 ohm characteristic impedance 19 4 Test Fixtures Balun Test Fixture with 200 MHz or greater bandwidth Appendix D 5 Load Fixture for Network Analyzer calibration Appendix A 5 19 5 Test Procedure 1 Insert CAT 5 cable from the UUT into transmitter side of Balun fixture and connect Balun to Network Analyzer with BNC cable as...

Page 84: ...rcuit Impedance Scope Parameters Settings Start Frequency 3 MHz Stop Frequency 13 MHz IF BW or Resolution BW Lowest practical bandwidth supported by equipment in the range of 100 KHz and 200 KHz Number of Points Resolution Maximum for instrument 401 Acquire Average if necessary Vertical Division 10 dB division Mode Network Analyzer Calculating Theoretical Return Loss To solve for theoretical retur...

Page 85: ...onfidential 75 10Base T TD Circuit Impedance Transmitter Return Loss 7 Set the marker to the worst case return loss between 5 MHz and 10 MHz inclusive The figure below provides a reference 8 Record the amplitude dB of the return loss 9 Verify the measurements meet specifications ...

Page 86: ...10Base T TD Circuit Impedance Transmitter Return Loss 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 76 Intel Confidential Note This page is intentionally left blank ...

Page 87: ... mV peak 20 3 Test Equipment Digitizing Oscilloscope 100 MHz or greater bandwidth Differential Probes 100 MHz or greater bandwidth Computer running Gigconf exe 20 4 Test Fixtures Test Fixture 14 14 Appendix D 6 20 5 Test Procedure 1 Insert test fixture into the UUT and attach differential probe and BNC cable to common mode terminals on the fixture as shown in Figure 20 1 Note It is important to pa...

Page 88: ...exe select the Common Mode Output 1411 10 09 test 3 Set scope settings for positive common mode measurement as shown in table below Differential Probe w 1 GHz BW Unit Under Test UUT Digitizing Oscilloscope Test Fixture 14 14 100 Ohm Resistive Load RX RJ 45 TX To Chassis GND can be metal shield on RJ 45 Table 20 1 Scope Configuration for TD Circuit Positive Common Mode Output Voltage Scope Paramete...

Page 89: ...ak Figure 20 2 Positive Peak Voltage Scope Reference 5 Record max peak positive amplitude value 6 Set scope settings for negative common mode measurement as shown in table below Table 20 2 Scope Configuration for TD Circuit Negative Common Mode Output Voltage Scope Parameter Setting Horizontal Scale 10 ns division Vertical Scale 80 mV to 80 mV at 8 divisions this equals 20 mV division Trigger Type...

Page 90: ...anual 80 Intel Confidential 7 Adjust trigger level until just triggering on signal Place cursor on maximum or peak voltage The figure below provides a negative peak reference Figure 20 3 Negative Peak Voltage Scope Reference 8 Record maximum or peak amplitude value s 9 Verify the measurements meet specifications ...

Page 91: ...nd twisted pair model shall be no more than 12 0 ns 21 3 Test Equipment Digitizing Oscilloscope 100 MHz or greater bandwidth Differential Probes 100 MHz or greater bandwidth CAT 5 twisted pair cable under 2 inches in length 21 4 Test Fixtures 100 Ω UTP test load Appendix A 1 Twisted pair model Appendix C 21 5 Test Procedure 1 Insert CAT 5 cable connected to twisted pair model into UUT and attach d...

Page 92: ...ype Pulse width 220 ns lower bound 320 ns upper bound Tight trigger 10 ns of actual pulse width is best Trigger Level Typically 0 5 V to 1 7 V Display Persistence Infinite persistence Pulse Width Triggering Triggering information is provided to give a good starting point for measurement The following guidelines will help the tester achieve the most stable display 1 Set the trigger level as specifi...

Page 93: ...ro crossing at 8 0 BT 7ns approximately 800 ns The graphic below provides a reference 5 Set vertical cursors to record the maximum closing of the eye The difference between the two cursors should be recorded as the jitter measurement 6 Shift waveform to the right and find zero crossing at 8 5 BT 7ns approximately 850 ns The graphic below provides a reference 8 0 Bit Times BT 8 5 Bit Times BT ...

Page 94: ... 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 84 Intel Confidential 7 Set vertical cursors to record maximum closing of the eye The difference between the two cursors should be recorded as the jitter measurement 8 Verify the measurements meet specifications ...

Page 95: ...0 Ω resistive load 22 2 Specification The jitter added to the signal on the DO circuit as it propagates through the UUT driving a 100 ohm resistive load shall be no more than 11 0 ns 22 3 Test Equipment Digitizing Oscilloscope 100 MHz or greater bandwidth Differential Probes 100 MHz or greater bandwidth CAT 5 twisted pair cable under 2 inches in length 22 4 Test Fixtures 100 Ω UTP test load Append...

Page 96: ...divisions use 320 mV division at 8 divisions 400 mV division Trigger Type Pulse width 220 ns lower bound 320 ns upper bound Tight trigger 10 ns of actual pulse width is best Trigger Level Typically 0 5 V to 1 7 V Display Persistence Infinite persistence Pulse Width Triggering Triggering information is provided to give a good starting point for measurement The following guidelines will help the tes...

Page 97: ...hic below provides a reference 5 Set vertical cursors to record the maximum closing of the eye The difference between the two cursors should be recorded as the jitter measurement 6 Shift the waveform to the right and find zero crossing at 8 5 BT 7 ns approximately 850 ns 7 Set vertical cursors to record the maximum closing of the eye The difference between the two cursors should be recorded as the...

Page 98: ...10Base T Transmitter Output Timing Jitter without Cable Model 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 88 Intel Confidential 8 Verify the measurements meet specifications ...

Page 99: ...or rate tests with specification compliant Category 5 cables across a range of lengths from approximately 1 meter to greater than 100 meters maximum specification Insertion loss measurements and propagation delay measurements have shown high quality Category 5 cable ranging from 115 m to 130 m may be equal to a maximum specification cable depending on the vendor and the cable manufacturing lot See...

Page 100: ...sults a Link partner Transmit Good Packets and Transmit Total Packets Both of these statistics should equal each other b UUT Receive Good Packets and Missed Packets 6 Calculate the bit error rate BER 7 Repeat steps 1 through 7 for each cable length 8 Verify the measurements meet specifications 23 6 Calculating Bit Error Rate BER The basic BER equation is as follows where TGP number of good frames ...

Page 101: ...the transmit unit Example 23 1 BER Calculation Example If 499 995 good frames were received and 500 000 good frames were transmitted then for 1 024 byte frames and zero missed packets the BER would be as follows BER 500 000 0 499 995 500 000 1 024 8 1 22 x 10 9 This example passes because the resulting BER is less than 1 x 10 8 which is the maximum specification It is recommended that the test ope...

Page 102: ...10Base T RD Receiver Circuit Signal Acceptance Test BER 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 92 Intel Confidential Note This page is intentionally left blank ...

Page 103: ... dB from 5 MHz to 10 MHz 24 3 Test Equipment Network Analyzer CAT 5 twisted pair cable under 2 inches in length BNC cable with 50 ohm characteristic impedance 24 4 Test Fixtures Balun Test Fixture with 200 MHz or greater bandwidth Appendix D 2 Load Fixture for Network Analyzer calibration Appendix A 5 24 5 Test Procedure 1 Insert CAT 5 cable from UUT into transmitter side of Balun fixture and conn...

Page 104: ...fferential Input Impedance Scope Parameter Setting Start Frequency 3 MHz Stop Frequency 13 MHz Resolution BW or IF BW Lowest practical bandwidth supported by equipment in the range of 10 KHz to 200 KHz Number of Points Resolution Maximum for instrument 401 Acquire Average if necessary Vertical Division 10 dB division Mode Network Analyzer Calculating Theoretical Return Loss To solve for theoretica...

Page 105: ...urn loss between 5 MHz and 10 MHz inclusive 8 Record the amplitude dB of the return loss 9 Verify the measurements meet specifications CH1 S11 LOG 5 dB REF 0 dB START 3 000 000 M Hz STOP 13 000 000 M Hz Cor Sm o Hld PRm 19 Mar 2002 18 46 18 1 2 3 3 37 130 dB 10 000 000 M Hz CH1 M ark ers 1 42 127 dB 5 00000 M Hz 2 37 130 dB 10 0000 M Hz NPPV Test Case 1411 11 05 UUTWestville_Anvik_A1_Fab3_10 100_b...

Page 106: ...0Base T RD Circuit Differential Input Impedance Receiver Return Loss 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 96 Intel Confidential Note This page is intentionally left blank ...

Page 107: ...n building test fixtures it is important to remember that an improper or unstable design may cause measurement errors Please refer to the IEEE specification for schematics for the needed test fixtures A 1 Fixture 40 25 Test fixture 40 25 terminates each channel with a 100 ohm load Each Resistor is 100 Ω 0 1 Ω A 100 Ω resistor across all four MDI signals must be present at the same time Angled side...

Page 108: ... is a CAT 5 cable with four pairs of square test pins with one pair on each differential pair within an inch of one of the male RJ 45 connectors A 3 Fixture 40 6 1 1 1 Test Cable This cable is used for master and slave transmit jitter IEEE 802 3 Section 40 6 1 2 5 It is made from three segments as defined in IEEE 802 3 Section 40 6 1 1 1 There are two segments with 120 ohm characteristic impedance...

Page 109: ...1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual Intel Confidential 99 1000Base T Test Fixtures and Calibration Load Fixtures ...

Page 110: ...e Tests Manual 100 Intel Confidential A 4 Fixture 40 8 3 1 A Fixture 40 8 3 1 A is a Balun test fixture A North Hills NH13732 or similar balun should be used A 5 Fixture 40 8 3 1 B Fixture 40 8 3 1 B is used to calibrate the network spectrum analyzer The illustration shows the network analyzer calibration loads ...

Page 111: ...able with four pairs of square pints mates to the Balun test fixture for return loss tests 100 ohm resistor loads are installed on the channels that are not being tested A 7 Fixture 40 28A Fixture 40 28A is used for the alien crosstalk noise rejection test It requires one half meter long CAT 5 cable with female test pins on the transmit differential positive and negative pins at one end The transm...

Page 112: ...are insulated from the copper ground plane by a layer of kapton tape The bottom row of right angle square pins are soldered to the copper ground plane diagram below shows the four solder joints in the bottom view just below Output V on the label The shield on the RJ 45 connector is soldered to the fixture s copper ground plane Note On the top side each top row square pin has a 49 9 ohm resistor so...

Page 113: ...ixture 40 32 s copper tape ground plane is soldered directly to the metal shield on the RJ 45 The fixture s RJ 45 shield connects to the UUT shielded connector The lower row of test pins are all connected to the UUT chassis ground indirectly through the fixture s copper ground plane Fixture 40 32 Top View Fixture 40 32 Bottom View Fixture 40 32 Side View ...

Page 114: ...4 Intel Confidential Figure 24 1 40 32 Schematic 1 2 2 1 1 2 49 9 Ohms 47 5 Ohms 47 5 Ohms A Pdf 1 2 2 1 1 2 2 1 49 9 Ohms 47 5 Ohms 47 5 Ohms B Pdf 1 2 2 1 1 2 2 1 49 9 Ohms 47 5 Ohms 47 5 Ohms C Pdf 1 2 2 1 1 2 2 1 49 9 Ohms 47 5 Ohms 47 5 Ohms D Pdf TXP SHIELD TXN RXP NC1 NC2 RXN NC3 NC4 SHIELD 1 2 3 4 5 6 7 8 2 1 RJ 45 Mate ...

Page 115: ...s of the differential pair around each other 4 Tightly toleranced components should be used wherever possible When using an ohm meter to cherry pick best resistor values subtract the meter s lead resistance from the measured resistance values As a starting point resistors should be 1 or better tolerance Use an ohm meter and select resistors that are within 0 1 Ω of the required value When a pair o...

Page 116: ...speeds RJ 45 Connector Pinout Pin 1 is channel A white orange wire Pin 2 is channel A orange wire Pin 3 is channel B white green wire Pin 6 is channel B green wire Pin 4 is channel C white blue wire Pin 5 is channel C blue wire Pin 7 is channel D white brown wire Pin 8 is channel D brown wire Contact pin Straight Through Cable Crossover Cable 1 A to A A to B 2 A to A A to B 3 B to B B to A 4 C to ...

Page 117: ...tel 6806 GigaMatch FTP 4P and Belden Belden YR44160 CM 4PR24 Shielded 1 Cut the cable preferably one of the cables mentioned above to the lengths specified in the IEEE 802 3ab specifications or this document 2 Trim the outer insulating jacket and shield back about 1 5 inches 3 Slide two four inch pieces of 3 8 inch or 1 2 inch diameter heat shrink tubing to the middle of the cable Do not heat or s...

Page 118: ...e Note This procedure has been used to construct unshielded 120 ohm impedance twisted pair cable However it is not recommended for the following reasons 1 The required calculations only approximate the desired target impedance They do not take into account the loading effects of the adjacent twisted pairs 2 It is labor intensive The individual pairs need to be twisted to a consistent number of twi...

Page 119: ...sec Quality CAT5 cable of segment L2 117 72632 meters of standard CAT5 cable is required for a 559 2 nsec delay Table C 3 Average Insertion Loss Comparison 16 MHz 31 25 MHz 50 MHz 80 MHz 100 MHz Quality CAT5 cable of 120 meters 8 61 12 22 15 62 20 08 22 73 Quality CAT5 cable of 117 7 meters 8 44 11 99 15 32 19 7 22 29 Constructed cable of 2 68 meters 0 18 0 24 0 33 0 48 0 46 Total Insertion Loss o...

Page 120: ...Worst Case Cable for Jitter 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 110 Intel Confidential Note This page is intentionally left blank ...

Page 121: ...dix D Other Test Fixtures D 1 100 Ohm UTP Test Load D 2 100Base TX Balun Test Fixture D 3 Open Circuit Inductance Test Fixture Note This is an optional test not currently documented 100 ohm 1 SMT Resistor soldered betwee two stake pins TX R D _ 1 0 0 1 0 0 Balun TD Balun RD RJ 45 50 ohm Balun 100 ohm 10 kohm pot 0 33uF ...

Page 122: ...Intel Confidential D 4 Receiver Common Mode Rejection Test Fixture Note This is an optional test not currently documented To Ethernet Receiver Unit Under Test Ecm input To Ethernet Traffic Generator Receiver Common Mode Rejection Test cable with two identical value resistors R1 R2 and 449 R 560 ...

Page 123: ... 45 Connector 1 2 3 6 North Hills Wideband Transformer Model 0300BB 100 ohm Bal 50 ohm Unb North Hills Wideband Transformer Model 0300BB 100 ohm Bal 50 ohm Unb 3 1 4 0 TD RD 47 5 ohms 47 5 ohms 49 9 ohms TD TD Ecm To Chasis Ground Text Fixture 14 14 Common Mode Output Voltage Test Circuit Alligator Clip Stake Pin Stake Pin RJ 45 Male Clear epoxy protective coating over the resistors 1 X 1 perf boa...

Page 124: ...Other Test Fixtures 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 114 Intel Confidential D 7 10BASE TX 14_7 Twisted Pair Model Figure D 1 10BASE TX 14_7 Twisted Pair Model ...

Page 125: ...ection is not an exhaustive treatment of this topic nor is it a replacement for a network analyzer s instruction manual E 1 1 Network Analyzer Setup and Calibration Measuring a cable with a network analyzer is relatively straightforward A vector network analyzer is more accurate than a scalar network analyzer Use two 50 ohm unbalanced to 100 ohm balanced transformers to match the cable impedance w...

Page 126: ...d isolation levels as absolute values If your analyzer displays an isolation insertion loss of 65 dB it is actually 65 dB unless you are measuring an amplifier or a device with greater than unity gain i e negative loss gain E 1 2 Measuring the Insertion Loss of the Twisted Pair Cable 10 Connect a known length preferably 50 meters or more of the twisted pair cable between the two baluns 100 ohm sid...

Page 127: ... Cable insertion loss can also be measured calculated by more difficult and or less accurate methods Signal generator two baluns and a couple of power meters Signal generator two baluns and an oscilloscope with one or two differential probes in lieu of one or both power meters Note A variation on the last method dispenses with the baluns and the differential probes but requires the use of two matc...

Page 128: ...uilding and Testing UTP LAN Cables to Insertion Loss Specifications 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 118 Intel Confidential Note This page is intentionally left blank ...

Page 129: ...mportant to avoid bends or other cable irregularities when performing tests since they can affect the impedance of twisted pair cables The following scope displays show the results of bending approximately 1 meter of CAT5 Twisted Pair Cable connected to a differential TDR plug in on a Tektronix 11801 oscilloscope Split Dot Cursor positions are fixed at the fifth and seventh graticles cursors at 23...

Page 130: ... 101 7 Cable with 2 diameter loop in cursor area Cursor 1 101 7 Cursor 2 101 4 Note A gentle bend has little affect Cable with half knot in cursor area Cursor 1 94 3 Cursor 2 96 3 Lower Z is caused by dielectric compression Conductors are closer together Half knot is untied straightened Cursor 1 112 2 Cursor 2 103 9 Higher Z is caused by bird cage effect Conductors are farther apart ...

Page 131: ... cable during sharp bends or separating the wires straightening after a sharp bend By compressing the dielectric between the two wires by 0 002 inches the cable impedance was decreased to 95 3 ohms at the point of compression This is similar to the impedance produced by the knot By separating the wires in the pair by 0 003 inches the cable impedance increased to 111 9 ohms at the point of separati...

Page 132: ...Reducing Measurement Error by Avoiding Cable Bending 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 122 Intel Confidential Note This page is intentionally left blank ...

Page 133: ...he correct channel has been selected on the scope Also confirm that the correct channel has been selected to be triggered on Verify that the test fixture s and scope are connected as shown in Make sure the scope probe is connected to the test fixture with the correct polarity Check that the host computer for the UUT has been booted under DOS and that phyconf exe is running Confirm that the UUT has...

Page 134: ...ilure is to follow Intel s reference schematic and board layout guidelines which can be found in the product design kit Many of the tests described in this document deal with the transmitter characteristics If the transmitter fails to meet specification the link partner s receiver may fail to correctly receive the signals resulting in high Bit Error Rates on the receiving unit G 3 Differential Out...

Page 135: ...and 15 pF depending on the design The required value of this capacitor is affected by both trace and magnetics capacitance G 5 Amplitude Symmetry ANSI specification 9 1 4 Incorrect amplitude symmetry can have a couple of undesired effects First it can decrease the distance apart two network stations can be before performance starts to seriously degrade Assume that the receiver can pick up a 1 V pe...

Page 136: ...rs should be routed at equal lengths from the PHY The sum of all segments in one trace should be equal to the sum of all segments of its corresponding differential pair in other words the sum of all TDP segments equals the sum of all TDN segments Also note that each trace in the differential pair should be run in parallel and on the same layer Splitting the traces onto two different layers will ca...

Page 137: ... signals Fortunately these types of signals are never as long as shown above so the problem will not usually be so dramatic that all of the packets will disappear Normally the extra inductance in the magnetics will improve the signals enough to prevent the majority of the errors G 9 Duty Cycle Distortion ANSI specification 9 1 8 Different receivers handle signals with duty cycle distortion differe...

Page 138: ... specification 9 1 9 Transmit jitter causes problems for the receiving unit because it becomes more difficult to distinguish the value of bits as jitter increases Systems with excessive jitter will therefore cause the receiving unit to have high Bit Error Rates There are several causes of jitter that can be addressed in board design and layout Noisy boards and poor common mode rejection will incre...

Page 139: ... designs to perform Bit Error tests since any problems with the transmitter on one unit will cause the receiver to have high BER G 12 Receiver Common Mode Rejection ANSI specification 9 2 3 Common mode noise is noise which affects both wires in the differential pair simultaneously and in phase Because it is the same across the pair it can be rejected by the receive unit The TP PMD spec defines tha...

Page 140: ... in the same differential pair Good power to ground decoupling is important around the PHY and out to the RJ 45 connector There are two types of decoupling capacitors high frequency and bulk The high frequency decoupling capacitors usually have a value of 0 1 µF and are placed throughout the board especially close to power ground and fast switching signals The bulk capacitors are used to keep the ...

Page 141: ...0021 Reg 9 0000 Reg 16 3C08 1411 10 03 Reg 0 8000 Reg 4 0021 Reg 9 0000 Reg 16 3C08 1411 10 07 Reg 0 8000 Reg 4 0021 Reg 9 0000 Reg 16 3C08 1411 10 09 Reg 0 8000 Reg 4 0021 Reg 9 0000 Reg 16 3C08 1411 10 12 Reg 0 8000 Reg 4 0021 Reg 9 0000 Reg 16 3C08 1411 10 13 Reg 0 8000 Reg 4 0021 Reg 9 0000 Reg 16 3C08 1411 11 05 Reg 0 8000 Reg 4 0021 Reg 9 0000 Reg 16 3C08 100Base Tx Register Settings 9 1 2 2...

Page 142: ...2 0809 Reg 0 1800 None None 9 1 5 Reg 0 2100 Reg 12 0809 Reg 0 1800 None None 9 1 6 Reg 0 2100 Reg 12 0809 Reg 0 1800 None None 9 1 8 Reg 0 2100 Reg 12 0808 Reg 0 1800 None None 9 1 9a Reg 16 41A0 Reg 18 0E00 Reg 0 2100 Reg 4 0101 Reg 9 1000 9 2 2a Reg 16 41A0 Reg 18 0E00 Reg 0 2100 Reg 4 0101 Reg 9 1000 1000Base T Register Settings 40 6 1 2 1 Reg 0 0140 Reg 9 3B00 None None None 40 6 1 2 2 Reg 0 ...

Page 143: ... 16 0F68 9 1 6 Please see the 82544 appendix 9 1 8 Please see the 82544 appendix 9 1 9 Reg 0 2100 Reg 4 0101 Reg 9 0000 None 9 2 2 Reg 0 2100 Reg 4 0101 Reg 9 0000 Reg 16 3B08 1000Base T Register Settings 40 6 1 2 1 Reg 16 0B08 Reg 0 8140 Reg 16 0F08 Reg 9 2200 40 6 1 2 2 Reg 16 0B08 Reg 0 8140 Reg 16 0F08 Reg 9 2200 40 8 3 1 Reg 16 0B08 Reg 0 8140 Reg 16 0F08 Reg 9 8200 40 8 3 3 Reg 16 0B08 Reg 0...

Page 144: ...Manual Register Settings 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 134 Intel Confidential Note This page is intentionally left blank ...

Page 145: ...ll possible to pulse width trigger on 100Base TX waveforms which are transmitted by the 82544 the constantly changing DC offsets cause a large amount of amplitude jitter in the acquired waveform Normally averaging reduces the level of jitter that is visible to the operator and averaging makes it easier to accurately place an oscilloscope s horizontal cursor on key parts of the 100Base TX pulse Unf...

Page 146: ...a PII desktop PC and was running phyconf exe rev 5 10 Beta 5 phyconf exe was used to force the 825444 UUT to transmit 100Base TX scrambled idles gigconf exe Software Register settings are provided in Appendix H 3 phyconf exe Software This software can be used if an Intel 10 100 LAN partner is used to transmit 100Base TX scrambled idles Register settings are provided in a separate document Test Fix...

Page 147: ... 82554 silicon I 3 5 Test Fixtures 100 Ohm UTP Test Load Fixture F9 1 2 A The test load shall consist of a single 100 ohm 0 1 resistor connected across the transmit pins of a mating RJ 45 connector The series inductance of the load shall not be greater than 20 nH and the parallel capacitance shall not be greater than 2 pF I 3 6 Test Procedure 1 Connect the Test equipment and Unit Under Test UUT as...

Page 148: ...vision Vertical Range 100 mV to 1100 mV 1200 mV over the full vertical scale Vertical Position 3 5 divisions to 4 0 divisions Trigger Type Positive Pulse Width Triggering 108 ns lower bound 116 ns upper bound Trigger Level 500 mV Trigger Signal Differential signal at the pins of the test load Table I 2 For Negative Peak Differential Output Amplitude see Figure I 4 Scope Parameter Setting Horizonta...

Page 149: ...een the average MLT 3 mid level 0 volts and the average peak positive output voltage This does not include overshoot If there is ripple or overshoot at either level the amplitude cursor may slice through it Although it is not specifically mentioned in specification 9 1 2 2 Vout should be between 950 mV and 1050 mV Figure I 3 and Figure I 3 provide examples of data for differential output voltage F...

Page 150: ...e time it takes for a signal to fall from either Vout or Vout back to the MLT 3 mid level 0 volts Rise and fall times for the positive differential output will be the time difference delta nsec between 10 of Vout and 90 of Vout Rise and fall times for the negative differential output will be the time difference delta nsec between 10 of Vout and 90 of Vout Note Note that measured rise and fall time...

Page 151: ...sec wide on both sides of the pulse AND for rise and fall times the operator must make several different plots with both horizontal cursors and cross hair cursors 1 Set the trigger level to 500 mV 2 Select Pulse Width triggering 3 Start with the upper bound at 118 nsec and the lower bound at 106 nsec 4 Set the Trigger Mode to NORMAL Scope Parameter Setting Horizontal Scale 1 ns division Vertical R...

Page 152: ...l acquisition mode to Single Sequence and or One Shot acquisition mode Do NOT use averaging Do NOT use sampling mode 12 Push the trigger button then scroll all the way to the left edge and all the way to the right edge of the captured pulse Note the MLT 3 mid level shoulders are they at least 20 nseconds wide Keep doing manual triggers until a pulse is acquired that has mid level shoulders on both...

Page 153: ...14 Scroll horizontally through the waveform until the right shoulder is occupying the width of the oscilloscope display Select the horizontal cursors Move one cursor to the top side of the mid level shoulder Move the other cursor to the bottom side of the mid level shoulder Record the values of both cursors See Figure I 7 and Figure I 8 Figure I 7 Lower right MLT 3 mid level lower cursor ...

Page 154: ...he average mid level from example Figure I 5 through Figure I 8 16 Scroll horizontally through the waveform until the approximate center of the pulse peak is visible on the oscilloscope display Select the horizontal cursors Move one cursor to the top of the ripple on the peak voltage Move the second cursor to the bottom of the ripple on the peak voltage The average of these two cursor levels is th...

Page 155: ...move the other cursor to 90 of Vout on the rising edge Rise time is the difference in time t between the two markers To measure the fall time position the cursors at 10 and 90 of Vout on the falling edge of the waveform Fall time is the difference in time t between the two markers Repeat these measurements on the negative going waveform Note Repeat all of these steps for both a positive pulse and ...

Page 156: ...op Peak Level mV Left shoulder top cursor 6 Positive Pulse top upper cursor 972 Left shoulder bottom cursor 42 Positive Pulse top lower cursor 941 Right shoulder top cursor 3 Averaged Pulse Peak Level mV 956 5 Right shoulder bottom cursor 36 Average MLT 3 mid level mV 21 75 10 voltage point on slope 0 1 x Averaged Peak Averaged mid level Averaged MLT 3 mid level 90 voltage point on slope 0 9 x Ave...

Page 157: ... 90 voltage points For the sake of brevity and to avoid repetition example plots are NOT provided for a negative pulse Repeat all of these steps for both a positive pulse and for a negative pulse I 4 8 9 1 6 Rise and Fall Times Measured Rise and Fall times shall be between 3 0 and 5 0 nsec Rise to Fall delta shall be 0 5 nsec Measured rise and fall times must be within the range between 3 0 nsec a...

Page 158: ...ecification When measured between 50 voltage points on Vout and Vout all positive pulse widths negative pulse widths and mid level time periods must be between 15 50 nsec and 16 50 nsec Note The specification wording within the ANSI TP PMD can be confusing but the illustration in the TP PMD clearly shows that 0 5 nsec variation is allowed I 5 4 Test Equipment Digitizing oscilloscope with at least ...

Page 159: ...a pattern creates16 nsec wide pulses If the above settings are implemented the Phy will automatically transmit 16ns wide pulses I 5 7 Generic Oscilloscope Settings Table I 5 For Duty Cycle Distortion Measurements 0 5 nsec 0 5 nsec 0 5 nsec 0 5 nsec 16 nsec 16 nsec 16 nsec Vout Vout 2 Vout 2 Vout Scope Parameter Setting Horizontal Scale 5 ns division and 2 ns division Vertical Range 1200 mV to 1200...

Page 160: ...e for the 82544 Chip 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 150 Intel Confidential Figure I 14 16 ns pulse peaks used to calculate 50 levels Figure I 15 Positive pulse width at 50 amplitude level ...

Page 161: ...e pulse widths and mid level time periods must be between 15 50 nsec and 16 50 nsec Interpretation the ANSI TP PMD version of this spec is somewhat confusing The text suggests the acceptable range for each pulse is 15 75 nsec to 16 25 nseconds but the 9 3 illustration in the specification clearly shows a range from 15 50 to 16 50 nsec We believe the illustration is correct and it helps to explain ...

Page 162: ...100Base TX Test Procedure for the 82544 Chip 1000BASE T 100BASE TX 10BASE T Physical Layer Compliance Tests Manual 152 Intel Confidential Note This page is intentionally left blank ...

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