Troubleshooting Guide
1000BASE-T/100BASE-TX/10BASE-T Physical Layer Compliance Tests Manual
126
Intel Confidential
Confirm that the resistors on TDN and TDP are identical (within 1%) and that they add up to 100
ohms. Also verify that the proper reference resistor values have been used.
G.6
Return Loss (ANSI specifications 9.1.5 and 9.2.2)
A system failing to meet return loss specifications indicates that substantial power is being
reflected. Reflections are typically related to an impedance mismatch between the PHY and the
transmit and receive signal traces. A system failing return loss would have a high BER on long
cables, short cables, or both.
Trace geometry is a key factor in determining the impedance of traces on a board, which directly
affect the design requirements. The proper impedance for both the transmit and the receive traces
should be verified. Many design tools will miscalculate board parameters which affect the trace
impedance. If the actual trace impedance is too low, the value can be improved by asking the board
manufacturer for trace impedances higher than 100 ohms. This should provide higher impedances
which are closer to 100 ohms.
If a capacitor is used between TDP and TDN to control rise time and overshoot, its value should not
be too large. If the capacitance is too large, it can result in low return loss.
Trace length is also very important. Transmit and receive differential pairs should be routed at
equal lengths from the PHY. The sum of all segments in one trace should be equal to the sum of all
segments of its corresponding differential pair (in other words, the sum of all TDP segments equals
the sum of all TDN segments). Also note that each trace in the differential pair should be run in
parallel and on the same layer. Splitting the traces onto two different layers will cause poor
common mode rejection.
G.7
Rise and Fall Times (ANSI specification 9.1.6)
Rise and fall times measure the time it takes for a pulse to rise to (and fall from) its peak amplitude.
Slow rise and/or fall times may cause narrow pulses not to reach their maximum amplitude.
Additionally, fast rise and/or fall times may increase the apparent width of the pulse and increase
overshoot.
Rise and fall times are most directly affected by the capacitance between TDN and TDP, which
includes both the capacitor and the trace capacitance. Increasing the capacitance increases the rise
and fall times. Decreasing the capacitance will decrease the rise and fall times. This capacitance
also has an impact on the transmitter return loss and overshoot. Increasing the capacitance
decreases the return loss, and vice versa. Increasing the capacitance also reduces overshoot, while
decreasing the capacitance increases overshoot. Experiment until a capacitance value is found that
produces the best results.
G.8
Open Circuit Inductance (ANSI specification 9.1.7)
Transformers only pass AC current. If the signal being transmitted stays at ‘1’ or ‘0’ for any great
length of time, it will begin to look like a DC signal to the transformer.
