IET Labs, Inc. RLC Digibridge 1693, User And Service Manual, Page: 133 / 171

109
1693 RLC Digibridge
Theory
4.2.4 The Dual-Slope Integrating
Detector and Converter
Circuitry
. Refer back to Figure 4-1 on page 106 and note
that the phase-sensitive detector/converter circuit
consists of a multiplier whose dc output is measured
by a dual-slope converter, providing the measurement
in digital form . The multiplier is a multiplying D/A
converter whose “reference” input is the test signal
and whose digital controls are signals representing a
stepwise approximation of a reference sine wave at
the test frequency. The dc value of the multiplier out-
put is proportional to the product of signal magnitude
multiplied by the cosine of the phase angle between
the test signal and the reference sine wave.
The dual-slope converter includes these three stages:
dual-slope integrator, comparator, and counter (all
controlled by the microprocessor through PIAs). In
the dual-slope integrator, a capacitor is charged for
a controlled integration time interval (sampling) at
a rate proportional to the multiplier output voltage.
This capacitor is then discharged at a fixed rate (the
deintegration slope) to zero voltage, a condition that
is sensed by a comparator. (See signal name “CMP-L”
on the block diagram.) Thus, the integrator and com-
parator transform the sampled dc output from the
multiplier into a precise interval of time.
The dual-slope measurement counter is gated by this
time interval, thus converting it into a digital number,
which is a principal data input to the microprocessor.
If the integration time is relatively long, so that the
integration capacitor voltage reaches a certain refer-
ence level, another comparator triggers the beginning
of the return (deintegration) slope before sampling
has been completed. (See signal name “BIG-L” on
block diagram.) The detector is then sampling and
converting simultaneously for a portion of the dual-
slope conversion cycle.
Data Acquisition Time . Data acquisition time includes
pauses for synchronization, and several integration/
deintegration cycles.
A pause for synchronization varies depending on
timing relationships among the START signal, length
of settling time or programmed delay, length of the
previous integration/deintegration cycle, and the
Digibridge clocks (particularly FCOUNT, shown on
block diagram). This pause can be as much as one
test-frequency period for high frequencies or up to
1/32 of the test-frequency period for low frequencies.
The integration (sampling, gate, or capacitor charg-
ing) time of the dual-slope integrator is the number
of full periods of the test frequency whose sum is
closest to (4 ms)x(integration-time factor) for FAST,
closest to but not over (16.7 ms)x(integration-time
factor) for MEDIUM, or closest to but not over 100
ms for SLOW measurement rate. (The integration-
time factor is normally 1.0 but can be programmed
between 0.25 and 6.)
The return (deintegration) time depends on the dc
voltage being converted and whether “BIG-L” has
been triggered (see above); therefore, this time re-
quirement varies in a complex manner.
Data acquisition includes several complete dual-slope
conversion cycles, with the reference sine wave at
3 or 4 different phases, exactly 90 degrees apart, as
follows:
For FAST and MEDIUM rates, 6 cycles (2 each
with reference phases of 0,90, and 180).
For FAST and MEDIUM rates if “quick acquisi-
tion” special function is enabled, 5 cycles.
For SLOW measurement rate, 8 cycles (2 each with
ref phases of 0, 90, 180, and 270).
Therefore, data acquisition time is a complex, dis-
continuous function of test frequency, the selected
measurement rate, programmed integration-time
factor, enabling or disabling of “quick acquisition”,
and pauses for synchronization.