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©2018 Integrated Device Technology, Inc
September 12, 2018
8A3xxxx Family Programming Guide
Serial Port Overview
The 8A3xxxx family supports up to 3 serial ports. One is a dedicated
I
2
C
Master port used for loading configuration data at reset and the other
two are configurable slave
I
2
C
or SPI ports that can be used at any time after the reset sequence is complete to monitor and/or configure the
device. In some variants of the device, the
I
2
C
Master port share pins with an
I
2
C
slave port.
Operation of the
I
2
C Master Port is only used by the device to access an external serial EEPROM and so won’t be discussed here.
Two slave ports have been provided to allow independent access to any of the device’s internal registers. This allows high priority accesses
not to be queued behind lower priority ones on a shared external serial interface. Note that internal to the device, both slave serial ports
access a single instance of each register over a shared internal bus. The device ensures that a burst access on one bus will complete
atomically once begun, before the other port can gain access to the shared internal bus or registers. However it does not guarantee the order
in which the two serial ports will be granted access to any shared resource.
Please refer to the appropriate section below for details on the operation of the slave
I
2
C or SPI
ports.
Either slave port can be reconfigured over either serial port at any time by accessing the appropriate registers. This includes both configuration
options with each protocol or switching between protocols (
I
2
C to SPI or vice versa). However it is recommended that the full operating mode
configuration, including page sizes for registers, for each serial port be set in the initial configuration data read from OTP or external EEPROM
(see Device Initial Configuration in the 8A3xxxx Datasheet for details).
Addressing Registers within a Device
The address space that is externally accessible within the
device is 64kbytes in size and so needs 16-bits of address offset information to be
provided during slave serial port accesses. Of that 64kbytes, only the upper 32kbytes contains user accessible registers.
The user may choose to operate either serial port providing the full offset address within each burst or to operate in a paged mode where part
of the address offset is provided in each transaction and part comes from an internal page register in each serial port. The decision may be
made independently on each slave serial port and each slave serial port has its own page register to avoid conflicts.
shows how page
register and offset bytes from each serial transaction interact to address a register within the 8A3xxxx.
Figure 1: Register Addressing Modes via Serial Port
I
2
C Slave Operation
The I
2
C slave protocol of the 8A3xxx family complies with
Version 2.1 of the I
2
C specification
shows the sequence of states on the
I
2
C SDATA signal for the supported modes of operation.
