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©2018 Integrated Device Technology, Inc
September 12, 2018
8A3xxxx Family Programming Guide
FRAME_SYNC_RESAMPL
E_EN[5]
R/W
0
Re-sample enable.
Enabling re-sample will have the frame/sync input signal being re-sampled by
the input reference clock (refclk). It can help to re-align the frame/sync with
respect to the refclk.
Ex. If the frame/sync input is aligned to the rising edge of the refclk, it might get
into the situation where it is uncertain whether the phase detector sees the
frame edge before or after the refclk edge. Re-sampling the frame/sync with the
falling edge of the refclk will get the frame/sync out of this situation.
0 = disabled
1 = enabled
FRAME_SYNC_PULSE[4:
0]
R/W
0
Select the reference input that is a frame or sync pulse to this input.
Selects either the input clock or PPS from the PWM decoder.
Selecting itself puts the DPLL back to normal tracking mode (i.e.. not in
frame/pulse mode).
0x00 = CLK0
0x01 = CLK1
0x02 = CLK2
0x03 = CLK3
0x04 = CLK4
0x05 = CLK5
0x06 = CLK6
0x07 = CLK7
0x08 = CLK8
0x09 = CLK9
0x0A = CLK10
0x0B = CLK11
0x0C = CLK12
0x0D = CLK13
0x0E = CLK14
0x0F = CLK15
0x10 = PPS from PWM Decoder 0
0x11 = PPS from PWM Decoder 1
0x12 = PPS from PWM Decoder 2
0x13 = PPS from PWM Decoder 3
0x14 = PPS from PWM Decoder 4
0x15 = PPS from PWM Decoder 5
0x16 = PPS from PWM Decoder 6
0x17 = PPS from PWM Decoder 7
0x18 = PPS from PWM Decoder 8
0x19 = PPS from PWM Decoder 9
0x1A = PPS from PWM Decoder 10
0x1B = PPS from PWM Decoder 11
0x1C = PPS from PWM Decoder 12
0x1D = PPS from PWM Decoder 13
0x1E = PPS from PWM Decoder 14
0x1F = PPS from PWM Decoder 15
INPUT_0.IN_SYNC Bit Field Descriptions
Bit Field Name
Field Type Default Value
Description