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©2018 Integrated Device Technology, Inc
September 12, 2018
8A3xxxx Family Programming Guide
Figure 2: I
2
C Slave Sequencing Diagram
The Dev Addr shown in the figure represents the base address of the
8A3xxxx
device. This 7-bit value can be set in an internal register which
can have a user-defined value loaded at reset from internal OTP memory or an external EEPROM. The default value if those methods are not
used is 0000000 (binary). Note that the levels on the S_A0 and S_A1 inputs can be used to control Bit 0 and Bit 1 (respectively) of this address.
These pins are available independently for each serial port. In I
2
C operation these inputs are expected to remain static. They have different
functions when the part is in SPI mode. The resulting base address is the I
2
C bus address that this device will respond to. The default address
may be over-written at any time.
When I
2
C operation is selected for either slave serial port, selection of 1-byte (1B) or 2-byte (2B) offset addressing must also be selected
independently for each slave serial port. These offsets are used in conjunction with the page register for each serial port to access registers
internal to the device. Because the I
2
C protocol already includes a read/write bit with the Dev Addr, all bits of the 1B or 2B offset field can be
used to address internal registers.
▪
In 1B mode, the lower 8-bits of the register offset address come from the Offset Addr byte and the upper 8-bits come from the page register
(see
for description of the 8-bit I
2
C Page Register).
The page register can be accessed at any time, no matter what page the serial port is currently on, using an offset byte value of FCh. This
4-byte register must be written in a single burst write transaction. The page register is replicated on every register page to always be
accessible.
▪
In 2B mode, the full 16-bit register address can be obtained from the Offset Addr bytes, so the page register only needs to be set once after
reset using a 3-byte burst access starting from address FFFDh (see
for description of the 16-bit I
2
C Page Register).
Table 2: I
2
C 1B Mode Page Register Bit Field Locations and Descriptions
Offset
Address
(Hex)
I
2
C 1B Mode Page Register Bit Field Locations
D7
D6
D5
D4
D3
D2
D1
D0
FC
PAGE_ADDR[7:0]
FD
PAGE_ADDR[15:8]
FE
PAGE_ADDR[23:16]
FF
PAGE_ADDR[31:24]
Sequential 16-bit Read
S
Dev Addr + W
A
Data X
A
Data X+1
A
A
Data X+n
A
Offset Addr X
MSB
A
Sr
Dev Addr + R
A
Sequential 16-bit Write
S
Dev Addr + W
A
Data X
P
A
Data X+1
A
A
Data X+n
A
from master to slave
from slave to master
Offset Addr X
MSB
A
S = start
Sr = repeated start
A = acknowledge
A = non-acknowledge
P = stop
Sequential 8-bit Read
S
Dev Addr + W
A
Data X
A
Data X+1
A
A
Data X+n
A
P
Offset Addr X
A
Sr
Dev Addr + R
A
Sequential 8-bit Write
S
Dev Addr + W
A
Data X
P
A
Data X+1
A
A
Data X+n
A
Offset Addr X
A
Offset Addr X
LSB
A
Offset Addr X
LSB
A
