IBM MPC603EC User Manual Download Page 14

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603 Hardware Specifications, REV 2

Preliminary—Subject to Change without Notice

1.4 Pinout Diagram

Figure 9 contains the pin assignments for the 603.

Figure 9. PowerPC 603 Microprocessor Pin Assignments

GBL
A1
A3
VDD
A5
A7
A9
OGND
GND
OVDD
A11
A13
A15
VDD
A17
A19
A21
OGND
GND
OVDD
A23
A25
A27
VDD
DBWO
DBG
BG
AACK
GND
A29
QREQ
ARTRY
OGND
VDD
OVDD
ABB
A31
DP0
GND
DP1
DP2
DP3
OGND
VDD
OVDD
DP4
DP5
DP6
GND
DP7
DL23
DL24
OGND
OVDD
DL25
DL26
DL27
DL28
VDD
OGND

TT4
A0
A2
VDD
A4
A6
A8
OVDD
GND
OGND
A10
A12
A14
VDD
A16
A18
A20
OVDD
GND
OGND
A22
A24
A26
VDD
DRTRY
TA
TEA
DBDIS
GND
A28
XATS
TS
OVDD
VDD
OGND
DBB
A30
DL0
GND
DL1
DL2
DL3
OVDD
VDD
OGND
DL4
DL5
DL6
GND
DL7
DL8
DL9
OVDD
OGND
DL10
DL11
DL12
DL13
VDD
OVDD

1
2
3
4
5
6
7
8
9

12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121

VDD

GND

OGND

TBEN

TLBISYNC

RSR

AP0

AP1

VDD

OGND

AP2

AP3

CSE

TC0

TC1

VDD

CLK_OUT

OGND

APE

DPE

CKSTP_OUT

CKSTP_IN

HRESET

PLL_CFG0

SYSCLK

PLL_CFG1

PLL_CFG2

VDD

PLL_CFG3

VDD

GND

LSSD_MODE

L1_TSTCLK

L2 _TSTCLK

TRST

TCK

TMS

TDI

TDO

TSIZ0

TSIZ1

TSIZ2

VDD

OGND

TBST

TT0

TT1

SRESET

INT

SMI

MCP

TT2

TT3

VDD

GND

OGND

240

239

238

237

236

235

234

233

232

231

230

229

228

227

226

225

224

223

222

221

220

219

218

217

216

215

214

213

212

211

210

209

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

VDD

DL29

DL30

DL31

GND

DH31

DH30

DH29

OGND

VDD

DH28

DH27

DH26

DH25

DH24

DH23

OGND

DH22

VDD

DH21

DH20

DH19

DH18

DH17

DH16

OGND

DH15

VDD

DH14

DH13

DH12

DH11

DH10

DH9

OGND

VDD

DH8

DH7

DH6

DL22

DL21

DL20

OGND

VDD

DL19

DL18

DL17

DH5

DH4

DH3

OGND

VDD

DH2

DH1

DH0

GND

DL16

DL15

DL14

OGND

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

TOP VIEW

Summary of Contents for MPC603EC

Page 1: ...ocessor is an implementation of the PowerPC family of reduced instruction set computer RISC microprocessors This document contains pertinent physical characteristics of the 603 For functional characte...

Page 2: ...ndependent on chip 8 Kbyte two way set associative physically addressed caches for instructions and data and on chip instruction and data memory management units MMUs The MMUs contain 64 entry two way...

Page 3: ...m 8 Kbyte instruction cache two way set associative physically addressed LRU replacement algorithm Cache write back or write through operation programmable on a per page or per block basis BPU that pe...

Page 4: ...ble 1 and Table 2 provide the absolute maximum ratings thermal characteristics and DC electrical characteristics for the 603 Table 1 Absolute Maximum Ratings Characteristic Symbol Value Unit Supply vo...

Page 5: ...ate leakage current Vin 3 465 V1 Vin 5 5 V1 ITSI 10 A ITSI TBD A Output high voltage IOH 9 mA VOH 2 4 V Output low voltage IOL 14 mA VOL 0 4 V Capacitance Vin 0 V f 1 MHz2 excludes TS ABB DBB and ARTR...

Page 6: ...Typical 2 0 mW 2 1 Typical 2 0 2 0 mW Note 1 The values provided for this mode do not include pad driver power OVDD or analog supply power AVDD Worst case AVDD 15 mW Table 5 Clock AC Timing Specificat...

Page 7: ...LK are reached during the power on reset sequence This specification also applies when the PLL has been disabled and subsequently re enabled during sleep mode Also note that HRESET must be held assert...

Page 8: ...for DRTRY QACK and TLBISYNC 0 0 0 0 0 ns 4 6 7 Notes 1 All input specifications are measured from the TTL level 0 8 or 2 0 V of the signal in question to the 1 4 V of the rising edge of the input SYSC...

Page 9: ...CLK frequencies Table 7 Output AC Timing Specifications Vdd 3 3 5 V dc GND 0 V dc CL 50 pF 0 TJ 105 C Num Characteristic 25 33 33 40 50 66 67 Unit Notes Min Max Min Max Min Max Min Max Min Max 12 SYSC...

Page 10: ...s are measured from the 1 4 V of the rising edge of SYSCLK to the TTL level 0 8 V or 2 0 V of the signal in question Both input and output timings are measured at the pin See Figure 4 2 All maximum ti...

Page 11: ...ions REV 2 11 Preliminary Subject to Change without Notice Figure 4 Output Timing Diagram SYSCLK 12 14 13 15 16 16 ALL OUTPUTS Except TS ABB TS ARTRY ABB DBB VM VM VM Midpoint Voltage 1 4 V DBB ARTRY...

Page 12: ...k pulse width measured at 1 4 V 25 ns 3 TCK rise and fall times 0 3 ns 4 TRST setup time to TCK rising edge 13 ns 1 5 TRST assert time 40 ns 6 Boundary scan input data setup time 6 ns 2 7 Boundary sca...

Page 13: ...ary scan timing diagram Figure 7 Boundary Scan Timing Diagram Figure 8 provides the test access port timing diagram Figure 8 Test Access Port Timing Diagram 4 5 TRST TCK 6 7 Input Data Valid 8 9 8 Out...

Page 14: ...152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 OVDD GND OGND CI WT QACK TBEN TLBISYNC RSRV AP0 AP1 OVDD OGND AP2 AP3 CS...

Page 15: ...I O AVDD 209 High Input BG 27 Low Input BR 219 Low Output CI 237 Low Output CLK_OUT 221 Output CKSTP_IN 215 Low Input CKSTP_OUT 216 Low Output CSE 225 High Output DBB 145 Low I O DBDIS 153 Low Input...

Page 16: ...28 138 148 163 173 183 194 222 229 240 High Input PLL_CFG0 PLL_CFG3 213 211 210 208 High Input QACK 235 Low Input QREQ 31 Low Output RSRV 232 Low Output SMI 187 Low Input SRESET 189 Low Input SYSCLK 2...

Page 17: ...that the 603 is currently offered in two types of CQFP packages the Motorola wire bond CQFP and the IBM C4 CQFP 1 6 1 Motorola Wire Bond CQFP Package Description The following sections provide the pac...

Page 18: ...chanical Dimensions of the Motorola Wire Bond CQFP Package Reduced pin count shown for clarity 60 pins per side Min Max A 30 86 31 75 B 34 6 BSC C 3 75 4 15 D 0 5 BSC E 0 18 0 30 F 3 10 3 90 G 0 13 0...

Page 19: ...ameters are as provided in the following list The package type is 32 mm x 32 mm 240 pin ceramic quad flat pack Package outline 32 mm x 32 mm Interconnects 240 Pitch 0 5 mm Lead plating Ni Au Solder jo...

Page 20: ...Figure 11 Mechanical Dimensions of the IBM C4 CQFP Package Reduced pin count shown for clarity 60 pins per side Min Max A 31 8 32 2 B 34 4 34 8 C 3 05 3 15 D 0 45 0 55 E 0 18 0 28 Clip Leadframe Chip...

Page 21: ...d should not exceed 200 MHz 2 In PLL bypass mode the SYSCLK input signal clocks the internal processor directly the PLL is disabled and the bus mode is set for 1 1 mode operation This mode is intended...

Page 22: ...close as possible to their associated Vdd pin Surface mount tantulum or ceramic devices are preferred It is also recommended that these decoupling capacitors receive their power from Vdd and GND powe...

Page 23: ...he device In this environment it can be assumed that all the heat is dissipated to the ambient through the heat sink so the junction to ambient thermal resistance is the sum of the resistances from th...

Page 24: ...Thermal resistance junction to heat sink R js or js 1 1 C Watt junction to heat sink 1 7 6 2 Thermal Management Example The following example is based on a typical desktop configuration using an IBM...

Page 25: ...the reliability limits of the device Notes 1 Junction to ambient thermal resistance is based on modeling 2 Junction to heat sink thermal resistance is based on measurements and model using thermal tes...

Page 26: ...6 provides a detailed description of the IBM part number for the 603 Figure 16 IBM Part Number Key Table 11 Ordering Information for the PowerPC 603 Microprocessor Package Type Internal Frequency Bus...

Page 27: ...follows Heat sink adhesive AIEG 7655 IBM reference drawing 99F4869 Test socket Yamaichi QFP PO 0 5 240P Signal 165 Power ground 75 Total 240 A 1 Package Environmental Operation Shipment and Storage Re...

Page 28: ...mbly process no solvent can be used with the C4FP and no more than 3 Kg of force must be applied normal to the top of the package prior to during or after card assembly Other details of the card assem...

Page 29: ...om side pressure of 44 psig water temperature of 62 5 C 2 5 C dwell time of 48 seconds minimum water flow rate of 350 liters minute Wash chamber 2 top and bottom sprays minimum top side pressure of 32...

Page 30: ...erty rights nor the rights of others Neither Motorola nor IBM makes any claim warranty or representation express or implied that the products described in this manual are designed intended or authoriz...

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