603 Hardware Specifications, REV 2
21
Preliminary—Subject to Change without Notice
1.7 System Design Information
This section provides electrical and thermal design recommendations for successful application of the 603.
1.7.1 PLL Configuration
A 603 part number corresponds to a particular combination of internal (CPU core) and SYSCLK (external
bus) frequency ranges which the device has been tested to. The PLL is configured by the
PLL_CFG0–PLL_CFG3 pins. For a given SYSCLK (bus) frequency, the PLL configuration pins set the
internal CPU frequency of operation.
Notes: 1. Some PLL configurations may select bus, CPU, or PLL frequencies which are not useful, not
supported, or not tested for by the 603. PLL frequencies (shown in parenthesis in Table 10) should
not fall below 133 MHz, and should not exceed 200 MHz.
2.
In PLL bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is
disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use
only. Note that the AC timing specifications given in this document do not apply in PLL bypass
mode.
3.
In clock-off mode, no clocking occurs inside the 603 regardless of the SYSCLK input.
4.
PLL_CFG0–PLL_CFG1 signals select the CPU-to-bus ratio (1:1, 2:1, 3:1, 4:1),
PLL_CFG2–PLL_CFG3 signals select the CPU-to-PLL multiplier (x2, x4, x8).
Table 10. PLL Configuration
Bus, CPU, and PLL Frequencies
PLL_CFG
0–3
CPU/
SYSCLK
Ratio
Bus
16.6 MHz
Bus
20 MHz
Bus
25 MHz
Bus
33.3 MHz
Bus
40 MHz
Bus
50 MHz
Bus
66.6 MHz
00 00
1:1
—
—
—
—
—
—
66.6
(133)
0001
1:1
—
—
—
33.3
(133)
40
(160)
50
(200)
—
0010
1:1
16.6
(133)
20
(160)
25
(200)
—
—
—
—
0100
2:1
—
—
—
66.6
(133)
80
(160)
100
(200)
—
0101
2:1
33.3
(133)
40
(160)
50
(200)
—
—
—
—
1000
3:1
—
—
75
(150)
100
(200)
—
—
—
1001
3:1
50
(200)
—
—
—
—
—
—
1100
4:1
66.6
(133)
80
(160)
100
(200)
—
—
—
—
1101
4:1
—
—
—
—
—
—
—
0011
PLL bypass
1111
Clock off