IBM 7015-R50, Installation And Service Manual

Page: 235 / 300

SystemGuard Test Groups
A-13
Walking 0 Data Test This test isolates the open lines among the data lines. It writes “0s
among 1s” pattern on the cache line. Then it is read and compared.
Transfer Modes On DCB Test
This sub-test is used to check the transfer of 1 to 8 bytes to the
memory. Initially the working area is written with 0s (blanked). Then
a byte is written and placed in the 8 possible locations of the long
word. This is read and compared with the written word for possible
errors.
Address Lines Accessibility Test
This test checks all the address lines access to the main memory, through the SMC ASIC.
The following hardware parts are checked by running this test.
1. SMC ASIC
2. Connection of address lines between CPU cards and System Planar ASICs
3. Connection of address lines between System Planar ASICs and memory chips.
This test consists of three sub-tests. Words manipulated / used are not restored at the end
of the test. This test applies to one of the four memory cards. In case of errors, suitable error
messages are displayed on the console. The following is a description of the sub-tests.
Work Area Test This subtest is used to find the working area safe enough to perform
the other tests. It first calculates the memory location and 0s are
written on the first long word and verified. Then 1s are written and
verified. If the verification is OK, the sub-test is ended and the next
sub-test is started.
When the test is run automatically during Power On, the next
sub-test are started, only if the results of this verification is OK.
Walking 1 Address Test
This test basically identifies if any address lines are stuck at level 0
or to any other address/data lines. This test writes two defined set
of patterns and the same are read and verified. If it is OK, the
process is repeated with the “1” bit shifted to the end of the working
area. Then the patterns are interchanged and written. If there is
any mismatch between the written word and the read word, suitable
error message is displayed.
Walking 0 Address Test
This test isolates the open lines among the address lines. It writes
two defined set of patterns and the same are read and verified. If it
is OK, the process is repeated with the “0” bit shifted to the
beginning of the working area. Then the patterns are interchanged
and written. If there is any mismatch between the written word and
the read word, suitable error message is displayed.
Memory Boards Decoding Test (MM BOARDS DEC TEST)
This test is performed by all the processors and checks the high order address line to the
main memory, through the DCB ASICs. The following hardware parts are checked by
running this test.
1. SMC ASIC (partially)
2. Connection of high order address lines between CPU cards and System Planar ASICs
3. Connection of high order address lines between System Planar ASICs and memory
chips.