Another way to approach the choice of sampling rate is to consider the
amount of margin designed into your system. Consider the following figure,
which shows a composite data output from a state machine in relation to the
system clock.
Data Output Relative to Clock
Here, we define the
margin
to be the ratio of the stable data time to unstable
data time. If the system margin is large, a sampling rate that is 4 times the
system clock rate is probably sufficient, but a sampling rate 10 times the
system clock rate will deliver best results.
If the margin is small, you will need to increase the sampling rate to at least
10 to 20 times the system clock rate; this ensures that you will have enough
data samples (3 or 4 during the stable data time) to determine whether your
system is behaving correctly. (If the margin is too small, it is likely that the
system works only intermittently or not at all.)
Figure 51
Ensuring Accurate Measurements
Glitch Detection
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Summary of Contents for 54620A
Page 7: ...6 ...
Page 13: ...12 ...
Page 17: ...16 ...
Page 18: ...1 Getting Started ...
Page 20: ...Using the Logic Analyzer Figure 1 Getting Started 19 ...
Page 52: ...2 Making Analyzer Measurements ...
Page 121: ...120 ...
Page 122: ...3 Solving Problems ...
Page 127: ...126 ...
Page 128: ...4 Ensuring Accurate Measurements ...
Page 150: ...5 Testing Adjusting and Troubleshooting the Analyzer ...
Page 180: ...6 Replaceable Parts ...
Page 193: ...Exploded View of Logic Analyzer Figure 60 Replaceable Parts To order a replacement part 192 ...
Page 196: ...7 Performance Characteristics ...
Page 208: ...8 Messages ...
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