HV100 Series High Performance Current Vector Inverter
94
Figure F7-7 Schematic diagram of frequency arrive
07.24
FDT1 detection mode
0
~
1
0
0: speed setting value
1: speed detection value
07.25
FDT1 level setting
0.00Hz
~【
00.13
】
upper limit frequency
50.00
07.26
FDT1 hysteresis value
0.0
~
100.0
%
*
【
07.25
】
2.0%
07.27
FDT2 detection mode
0
~
1
0
0: speed setting value
1: speed detection value
07.28
FDT2 level setting
0.00Hz
~【
00.13
】
upper limit frequency
25.00
07.29
FDT2 hysteresis value
0.0
~
100.0
%
*
【
07.28
】
4.0%
The above function codes (07.24 ~ 07.29) are supplementary descriptions for functions No.4 and No.5 of function
codes 07.18 ~ 07.21. When the output frequency of the inverter rises above the set value of FDT level, it outputs an valid
signal (open collector signal, which is low level after the resistor is pulled up). When the output frequency drops below FDT
signal (set value-hysteresis value), it outputs an invalid signal. As shown in the figure below:
Figure F7-8 Schematic diagram of frequency level detection
07.30
Processing in the Count arrival
0
~
3
3
Set frequency
FAR detection amplitude
Time
Time
Time
Time
FDT hysteresis value
Set value of FDT
level