GigaDevice Semiconductor GD32A50 Series, User Manual

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GD32A50x User Manual
514
Figure 20-10. Data setup time
SDA
SCL
SCLDELY
SCL stretched low by the I2C
t
SU;DAT
When the SCL falling edge is internally detected, a delay is inserted before sending SDA
output. This delay is t
SDADELY
= SDADELY * t
PSC
+ t
I2CCLK
where t
PSC
= (PSC+1) * t
I2CCLK
. t
SDADELY
effects t
HD;DAT
. The total delay of SDA output is t
SYNC1
+ {[SDADELY
* (PSC+1) + 1] * t
I2CCLK
}.
t
SYNC1
depends on SCL falling slope, the delay of analog filter, the delay of digital filter and
delay of SCL synchronization to I2CCLK clock. The delay of SCL synchronization to I2CCLK
clock is 2 to 3 t
I2CCLK
.
SDADELY must match condition as follows:
 SDADELY≥{t
f
(
max
)
+t
HD;DAT
(
min
)
-t
AF
(
min
)
-[(DNF+3)*t
I2CCLK
]}/[
(
PSC+1
)
*t
I2CCLK
]
 SDADELY≤{t
HD;DAT
(max)-t
AF
(
max
)
-[(DNF+4)*t
I2CCLK
]}/[
(
PSC+1
)
*t
I2CCLK
]
Note: t
AF
is the delay of analog filter. The t
HD;DAT
should be less than the maximum of
t
VD;DAT
.
When SS = 0, after t
SDADELY
delay, the slave had to stretch the clock before the data writing
to I2C_TDATA register, SCL is low during the data setup time. The setup time is
t
SCLDELY
=
(
1
)
*t
PSC
. t
SCLDELY
effects t
SU;DAT
.
SCLDELY must match condition as follows:
 SCLDELY≥{[t
r
(
max
)
+t
SU;DAT
(
min
)
]/[(PSC+1)*t
I2CCLK
]}-1
In master mode, the SCL clock high and low levels must be configured by programming the
PSC[3:0], SCLH[7:0] and SCLL[7:0] bits in the I2C_TIMING register.
When the SCL falling edge is internally detected, a delay is inserted before releasing the SCL
output. This delay is t
SCLL
=(SCLL+1)*t
PSC
where t
PSC
=
(
PSC+1
)
*t
I2CCLK
. t
SCLL
impacts the
SCL low time t
LOW
.
When the SCL rising edge is internally detected, a delay is inserted before forcing the SCL
output to low level. This delay is t
SCLH
=(SCLH+1)*t
PSC
where t
PSC
=
(
PSC+1
)
*t
I2CCLK
. t
SCLH
impacts the SCL high time t
HIGH
.
Note:
When the I2C is enabled, the timing configuration and SS mode must not be changed.