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GD32A50x User Manual

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bus idle condition (the sequence of 11 consecutive recessive bits) is detected. Refer to the

CAN Protocol standard (ISO 11898-1).

The protocol exception detection is controlled by PREEN bit in CAN_CTL2 register.

The edge filtering can be configured by EFDIS bit in CAN_CTL2 register, which is used during

the bus integration state. When the edge filtering is enabled, two consecutive nominal time

quanta with dominant bus state are required to detect an edge that causes synchronization.

When synchronization occurs, the counting for

bus idle condition (the sequence of 11

consecutive recessive bits

) is restarted. When edge filtering is performed, dominant bus-

states shorter than a nominal bit time (the bits in data phase of a FD frame) will be ignored,

stopped from being mistaken for an idle condition.

Refer to the CAN Protocol standard (ISO

11898-1).

Errors

If at least one of the error flags (ACKERR, BRERR, BDERR, CRCERR, FMERR, and

STFERR bit in CAN_ERR1 register

) is set, ERRSF bit in CAN_ERR1 register will be set. If

ERRSIE bit in CAN_CTL1 register is set, an error interrupt will be generated.

If at least one of the error flags (BRFERR, BDFERR, CRCFERR, FMFERR, and STFFERR

bit in CAN_ERR1 register

) is set, ERRFSF bit in CAN_ERR1 register will be set. If ERRFSIE

bit in CAN_CTL2 register is set, an error interrupt will be generated for errors detected in CAN
FD frame data phase with BRS bit set.

Acknowledge error

If there is only one node operating, then it will lead to TECNT[7:0] in CAN_ERR0 register
incrementing (to 128 at most by acknowledge error) in each message transmission, and an
acknowledge error will occur, which is indicated by ACKERR bit in the CAN_ERR1 register.

Bit recessive error

When at least one bit sent as recessive ‘1’ is received as dominant ‘0’, a bit recessive error

occurs. Refers to BRFERR and BRERR bit in CAN_ERR1 register.

Bit dominant error

When at least one bit sent as dominant ‘0’ is received as recessive ‘1’, a bit dominant error

occurs. Refers to BDFERR and BDERR bit in CAN_ERR1 register.

CRC error

When the calculated CRC is different from the received CRC field of the frame, a CRC error

occurs. Refers to CRCFERR and CRCERR bit in CAN_ERR1 register.

Form error

When a fixed-form bit field contains at least one illegal bit, a form error occurs. Refers to

FMFERR and FMERR bit in CAN_ERR1 register.

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Summary of Contents for GD32A50 Series

Page 1: ...GigaDevice Semiconductor Inc GD32A50x Arm Cortex M33 32 bit MCU User Manual Revision 1 0 Sep 2022 ...

Page 2: ...SYSCFG_EXTISS1 39 1 6 5 EXTI sources selection register 2 SYSCFG_EXTISS2 40 1 6 6 EXTI sources selection register 3 SYSCFG_EXTISS3 41 1 6 7 System configuration register 2 SYSCFG_CFG2 42 1 6 8 System status register SYSCFG_STAT 43 1 6 9 System configuration register 3 SYSCFG_CFG3 44 1 6 10 TIMER input source select register SYSCFG_TIMERINSEL 45 1 7 Device electronic signature 47 1 7 1 Memory densi...

Page 3: ..._STAT0 82 2 4 5 Control register 0 FMC_CTL0 83 2 4 6 Address register 0 FMC_ADDR0 85 2 4 7 Option byte unlock key register FMC_OBKEY 85 2 4 8 Unlock key register 1 FMC_KEY1 86 2 4 9 Status register 1 FMC_STAT1 86 2 4 10 Control register 1 FMC_CTL1 87 2 4 11 Address register 1 FMC_ADDR1 89 2 4 12 EEPROM counter register FMC_EPCNT 89 2 4 13 Option byte status register FMC_OBSTAT 90 2 4 14 Erase Prog...

Page 4: ...unit CCTL 113 5 2 1 Overview 113 5 2 2 Characteristics 115 5 2 3 Function overview 115 5 3 Register definition 120 5 3 1 Control register RCU_CTL 120 5 3 2 Configuration register 0 RCU_CFG0 122 5 3 3 Interrupt register RCU_INT 125 5 3 4 APB2 reset register RCU_APB2RST 128 5 3 5 APB1 reset register RCU_APB1RST 130 5 3 6 AHB enable register RCU_AHBEN 132 5 3 7 APB2 enable register RCU_APB2EN 133 5 3...

Page 5: ...rigger selection for ADC1 register TRIGSEL_ADC1 164 7 5 5 Trigger selection for DAC register TRIGSEL_DAC 165 7 5 6 Trigger selection for TIMER0_ITI register TRIGSEL_TIMER0IN 165 7 5 7 Trigger selection for TIMER0_BRKIN register TRIGSEL_TIMER0BRKIN 166 7 5 8 Trigger selection for TIMER7_ITI register TRIGSEL_TIMER7IN 167 7 5 9 Trigger selection for TIMER7_BRKIN register TRIGSEL_TIMER7BRKIN 168 7 5 1...

Page 6: ... A F 190 8 4 7 Port bit operate register GPIOx_BOP x A F 190 8 4 8 Port configuration lock register GPIOx_LOCK x A F 191 8 4 9 Alternate function selected register 0 GPIOx_AFSEL0 x A F 192 8 4 10 Alternate function selected register 1 GPIOx_AFSEL1 x A F 193 8 4 11 Bit clear register GPIOx_BC x A F 194 8 4 12 Port bit toggle register GPIOx_TG x A F 195 9 Multi function communication Interface MFCOM...

Page 7: ... MFCOM_TMCFGx 223 9 5 18 Timer compare x register MFCOM_TMCMPx 225 10 CRC calculation unit CRC 227 10 1 Overview 227 10 2 Characteristics 227 10 3 Function overview 228 10 4 Register definition 229 10 4 1 Data register CRC_DATA 229 10 4 2 Free data register CRC_FDATA 229 10 4 3 Control register CRC_CTL 230 10 4 4 Initialization data register CRC_IDATA 230 10 4 5 Polynomial register CRC_POLY 231 11...

Page 8: ...tiplexer channel interrupt flag register DMAMUX_RM_INTF 257 12 5 3 Request multiplexer channel interrupt flag clear register DMAMUX_RM_INTC 257 12 5 4 Request generator channel x configuration register DMAMUX_RG_CHxCFG 258 12 5 5 Request generator interrupt flag register DMAMUX_RG_INTF 259 12 5 6 Request generator interrupt flag clear register DMAMUX_RG_INTC 259 13 Debug DBG 261 13 1 Introduction ...

Page 9: ...fast mode 280 14 5 4 Routine follow up slow mode 280 14 6 ADC interrupts 281 14 7 Register definition 282 14 7 1 Status register ADC_STAT 282 14 7 2 Control register 0 ADC_CTL0 283 14 7 3 Control register 1 ADC_CTL1 285 14 7 4 Sample time register 0 ADC_SAMPT0 286 14 7 5 Sample time register 1 ADC_SAMPT1 287 14 7 6 Watchdog high threshold register 0 ADC_WDHT0 288 14 7 7 Watchdog low threshold regi...

Page 10: ...T_R8DH 302 15 4 6 DAC_OUT data output register OUT_DO 302 15 4 7 DAC Status register DAC_STAT 302 16 Watchdog timer WDGT 304 16 1 Free watchdog timer FWDGT 304 16 1 1 Overview 304 16 1 2 Characteristics 304 16 1 3 Function overview 304 16 1 4 Register definition 307 16 2 Window watchdog timer WWDGT 311 16 2 1 Overview 311 16 2 2 Characteristics 311 16 2 3 Function overview 311 16 2 4 Register defi...

Page 11: ...iew 420 18 2 2 Characteristics 420 18 2 3 Block diagram 420 18 2 4 Function overview 421 18 2 5 Registers definition TIMERx x 1 437 18 3 Basic timer TIMERx x 5 6 460 18 3 1 Overview 460 18 3 2 Characteristics 460 18 3 3 Block diagram 460 18 3 4 Function overview 460 18 3 5 Registers definition TIMERx x 5 6 464 19 Universal synchronous asynchronous receiver transmitter USART 469 19 1 Overview 469 1...

Page 12: ...RDATA 504 19 4 11 Transmit data register USART_TDATA 505 19 4 12 USART coherence control register USART_CHC 505 19 4 13 USART receive FIFO control and status register USART_RFCS 506 20 Inter integrated circuit interface I2C 508 20 1 Overview 508 20 2 Characteristics 508 20 3 Function overview 508 20 3 1 Clock requirements 509 20 3 2 I2C communication flow 510 20 3 3 Noise filter 513 20 3 4 I2C tim...

Page 13: ...ming and data format 550 21 3 4 NSS function 551 21 3 5 SPI operating modes 552 21 3 6 DMA function 561 21 3 7 CRC function 561 21 3 8 SPI interrupts 562 21 4 I2S function overview 563 21 4 1 I2S block diagram 563 21 4 2 I2S signal description 564 21 4 3 I2S audio standards 564 21 4 4 I2S clock 572 21 4 5 Operation 573 21 4 6 DMA function 577 21 4 7 I2S interrupts 577 21 5 Register definition 579 ...

Page 14: ...611 23 3 5 Data transmission 612 23 3 6 Data reception 616 23 3 7 Data reception in Pretended Networking mode 623 23 3 8 CAN FD operation 626 23 3 9 Errors and states 629 23 3 10 Communication parameters 632 23 3 11 Interrupts 635 23 4 Example for a typical configuration flow of CAN 635 23 5 CAN registers 638 23 5 1 Control register 0 CAN_CTL0 638 23 5 2 Control register 1 CAN_CTL1 640 23 5 3 Time...

Page 15: ...dentifier filter expected identifier 1 register CAN_PN_IFEID1 659 23 5 23 Pretended Networking mode data 0 filter expected data high 0 register CAN_PN_DF0EDH0 659 23 5 24 Pretended Networking mode data 1 filter expected data high 1 register CAN_PN_DF1EDH1 660 23 5 25 Pretended Networking mode received wakeup mailbox x control status information register CAN_PN_RWMxCS x 0 3 661 23 5 26 Pretended Ne...

Page 16: ...7 Figure 8 1 Basic structure of a general pupose I O 178 Figure 8 2 Basic structure of Input configuration 180 Figure 8 3 Basic structure of Output configuration 180 Figure 8 4 Basic structure of Analog configuration 181 Figure 8 5 Basic structure of Alternate function configuration 182 Figure 9 1 MFCOM block diagram 196 Figure 9 2 Shifter microarchitecture 198 Figure 10 1 Block diagram of CRC cal...

Page 17: ...f down counting mode change TIMERx_CAR on the go 332 Figure 18 8 Timing chart of center aligned counting mode 334 Figure 18 9 Repetition counter timing chart of center aligned counting mode 335 Figure 18 10 Repetition counter timing chart of up counting mode 335 Figure 18 11 Repetition counter timing chart of down counting mode 336 Figure 18 12 Channel 0 input capture principle 337 Figure 18 13 Mu...

Page 18: ... go 424 Figure 18 47 Timing chart of down counting mode PSC 0 2 425 Figure 18 48 Timing chart of down counting mode change TIMERx_CAR on the go 426 Figure 18 49 Timing chart of center aligned counting mode 427 Figure 18 50 Channels input capture principle 428 Figure 18 51 Channel output compare principle x 0 1 2 3 429 Figure 18 52 Output compare under three modes 430 Figure 18 53 EAPWM timechart 4...

Page 19: ... address Master Receive when HEAD10R 1 512 Figure 20 9 Data hold time 513 Figure 20 10 Data setup time 514 Figure 20 11 Data transmission 516 Figure 20 12 Data reception 516 Figure 20 13 I2C initialization in slave mode 519 Figure 20 14 Programming model for slave transmitting when SS 0 520 Figure 20 15 Programming model for slave transmitting when SS 1 521 Figure 20 16 Programming model for slave...

Page 20: ...d timing diagram DTLEN 10 CHLEN 1 CKPL 1 567 Figure 21 27 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 0 567 Figure 21 28 MSB justified standard timing diagram DTLEN 01 CHLEN 1 CKPL 1 567 Figure 21 29 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 567 Figure 21 30 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 567 Figure 21 31 LSB justified standard tim...

Page 21: ...PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 571 Figure 21 49 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 0 571 Figure 21 50 PCM standard long frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 572 Figure 21 51 Block diagram of I2S clock generator 572 Figure 21 52 I2S initialization sequence 574 Figure 21 5...

Page 22: ... 75 Table 2 13 OB_DFWP bit for pages protected EFALC 0x3 0xC 0xE 75 Table 2 14 OB_EPWP bit for protected 76 Table 2 15 PGSERR conditions 77 Table 2 16 PGAERR conditions 78 Table 2 17 PGERR conditions 78 Table 2 18 WPERR conditions 78 Table 3 1 Power saving mode summary 101 Table 5 1 Clock source select 118 Table 5 2 Core domain voltage selected in Deep sleep mode 119 Table 6 1 NVIC exception types...

Page 23: ...f slave mode 433 Table 19 1 Description of USART important pins 470 Table 19 2 Configuration of stop bits 472 Table 19 3 USART interrupt requests 486 Table 20 1 Definition of I2C bus terminology refer to the I2C specification of Philips semiconductors 509 Table 20 2 Data setup time and data hold time 515 Table 20 3 Communication modes to be shut down 516 Table 20 4 SMBus with PEC configuration 529...

Page 24: ...x arbitration value 35 bit when local priority enabled 615 Table 23 9 Rx mailbox matching 621 Table 23 10 Rx FIFO matching 622 Table 23 11 Interrupt events 635 Table 23 12 Rx FIFO filter element number 649 Table 24 1 List of abbreviations used in register 667 Table 24 2 List of terms 667 Table 25 1 Revision history 669 ...

Page 25: ...e for market products that require microcontrollers with high performance and low power consumption The Cortex M33 processor is based on the Armv8 architecture and supports a powerful and scalable instruction set including general data processing I O control tasks advanced data processing bit field manipulations and DSP Some system peripherals listed below are also provided by Cortex M33 Internal ...

Page 26: ...as an ITM module it does not support the output of trace data 1 2 System architecture A 32 bit multilayer bus is implemented in the GD32A50x devices which enables parallel access paths between multiple masters and slaves in the system The multilayer bus consists of an AHB interconnect matrix one AHB bus and two APB buses The interconnection relationship of the AHB interconnect matrix is shown belo...

Page 27: ...heral region DMA0 and DMA1 are the buses of DMA0 and DMA1 respectively There are also several slaves connected with the AHB interconnect matrix including FMC SRAM AHB1 AHB2 FMC is the bus interface of the flash memory controller SRAM is on chip static random access memories AHB1 is the AHB bus connected with all of the AHB slaves except GPIO AHB2 is the AHB bus connected with GPIO While APB1 and A...

Page 28: ...s A B C D E F BOR CMP TIMER7 TIMER19 APB2 F max 100MHz Powered by LDO 1 1V APB1 F max 50MHz TIMER5 6 I2C0 1 RTC WWDGT FWDGT USART1 2 Powered by VDD VDDA IRC40K 40KHz SPI1 I2S1 TIMER1 DAC PMU CBus SBus C SBus GP DMA1 7chs DMAMUX TRIGSEL SYSCFG 12 bit SAR ADC ADC1 CAN0 1 LXTAL 32 768kHz M F C O M 1 3 Memory map The Arm Cortex M33 processor is structured in Harvard architecture which can use separate...

Page 29: ...4000 0xE004 43FF DBG 0xE000 0000 0xE004 3FFF Cortex M33 internal peripherals External RAM 0x6000 0000 0x9FFF FFFF Reserved Peripheral AHB1 0x5000 0000 0x5FFF FFFF Reserved AHB2 0x4800 1800 0x4FFF FFFF Reserved 0x4800 1400 0x4800 17FF GPIOF 0x4800 1000 0x4800 13FF GPIOE 0x4800 0C00 0x4800 0FFF GPIOD 0x4800 0800 0x4800 0BFF GPIOC 0x4800 0400 0x4800 07FF GPIOB 0x4800 0000 0x4800 03FF GPIOA AHB1 0x400...

Page 30: ...001 2400 0x4001 27FF ADC0 0x4001 2000 0x4001 23FF Reserved 0x4001 1C00 0x4001 1FFF Reserved 0x4001 1800 0x4001 1BFF Reserved 0x4001 1400 0x4001 17FF Reserved 0x4001 1000 0x4001 13FF Reserved 0x4001 0C00 0x4001 0FFF Reserved 0x4001 0800 0x4001 0BFF Reserved 0x4001 0400 0x4001 07FF EXTI 0x4001 0000 0x4001 03FF SYSCFG APB1 0x4000 DC00 0x4000 FFFF Reserved 0x4000 D800 0x4000 DBFF Reserved 0x4000 D400 ...

Page 31: ...000 3000 0x4000 33FF FWDGT 0x4000 2C00 0x4000 2FFF WWDGT 0x4000 2800 0x4000 2BFF RTC 0x4000 2400 0x4000 27FF Reserved 0x4000 2000 0x4000 23FF Reserved 0x4000 1C00 0x4000 1FFF Reserved 0x4000 1800 0x4000 1BFF Reserved 0x4000 1400 0x4000 17FF TIMER6 0x4000 1000 0x4000 13FF TIMER5 0x4000 0C00 0x4000 0FFF Reserved 0x4000 0800 0x4000 0BFF Reserved 0x4000 0400 0x4000 07FF Reserved 0x4000 0000 0x4000 03F...

Page 32: ...ontain up to 48KB of on chip SRAM which starts at the address 0x2000 0000 It supports byte half word 16 bits and word 32 bits accesses ECC When reading and writing SRAM it supports 7 bit ECC function It can correct 1 bit error and detect multiple bits two bits error It must be written before reading SRAM otherwise it may cause ECC error Unaligned read operations will be performed in accordance wit...

Page 33: ...bit error correction event is detected in SRAM EEIC 1 The SRAMECCSEF bit int SYSCFG_CFG3 register will be set Software can clear it by writing 1 2 The SYSCFG_CFG3 records the address where the single bit error correction event occurred Two bits non correction error event When a two bits non correction error event is detected in SRAM EEIC 1 The SRAMECCMEF bit int SYSCFG_CFG3 register will be set So...

Page 34: ...e Boot mode selection pins Boot1 Boot0 Main Flash Memory x 0 System Memory 0 1 On chip SRAM 1 1 After power on sequence or a system reset the Arm Cortex M33 processor fetches the top of stack value from address 0x0000 0000 and the base address of boot code from 0x0000 0004 in sequence Then it starts executing code from the base address of boot code According to the selected boot source either the ...

Page 35: ...Manual 35 1 5 System configuration controller The main purposes of the system configuration controller SYSCFG are the following Remapping of some I O ports Managing the external interrupt line connection to the GPIOs ...

Page 36: ...function on the BOOT0 pin When BOOT0_PF0_RMP is set the BOOT0 function is tied to 0 by hardware after system reset In this case the system will boot from main flash without regard to the input value from the BOOT0 pin 0 No remap BOOT0 function is mapping on the BOOT0 pin 1 Remap PF0 function is mapping on the BOOT0 pin 5 Reserved Must be kept at reset value 4 PA9_PA12_RMP PA9 and PA12 remapping bi...

Page 37: ...9 is mapping on PC6 30 ADC0CH8RMP ADC0 channel 8 remapping bit 0 ADC0_IN8 is mapping on PB2 1 ADC0_IN8 is mapping on PC7 29 ADC1CH15RMP ADC1 channel 15 remapping bit 0 ADC1_IN15 is mapping on PB13 1 ADC1_IN15 is mapping on PD14 28 ADC1CH14RMP ADC1 channel 14 remapping bit 0 ADC1_IN14 is mapping on PB14 1 ADC1_IN14 is mapping on PD15 27 0 Reserved Must be kept at reset value 1 6 3 EXTI sources sele...

Page 38: ...erved 11 8 EXTI2_SS 3 0 EXTI 2 sources selection X000 PA2 pin X001 PB2 pin X010 PC2 pin X011 PD2 pin X100 PE2 pin X101 PF2 pin X110 reserved X111 reserved 7 4 EXTI1_SS 3 0 EXTI 1 sources selection X000 PA1 pin X001 PB1 pin X010 PC1 pin X011 PD1 pin X100 PE1 pin X101 PF1 pin X110 reserved X111 reserved 3 0 EXTI0_SS 3 0 EXTI 0 sources selection X000 PA0 pin X001 PB0 pin X010 PC0 pin X011 PD0 pin X10...

Page 39: ... rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI7_SS 3 0 EXTI 7 sources selection X000 PA7 pin X001 PB7 pin X010 PC7 pin X011 PD7 pin X100 PE7 pin X101 PF7 pin X110 reserved X111 reserved 11 8 EXTI6_SS 3 0 EXTI 6 sources selection X000 PA6 pin X001 PB6 pin X010 PC6 pin X011 PD6 pin X100 PE6 pin X101 PF6 pin X110 reserved X111 reserved 7 4 EXTI5_SS 3 0 EXTI 5 so...

Page 40: ...29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI11_SS 3 0 EXTI10_SS 3 0 EXTI9_SS 3 0 EXTI8_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EXTI11_SS 3 0 EXTI 11 sources selection X000 PA11 pin X001 PB11 pin X010 PC11 pin X011 PD11 pin X100 PE11 pin X101 reserved X110 reserved X111 reserved 11 8 EXTI10_SS 3 0 ...

Page 41: ...ed X111 reserved 1 6 6 EXTI sources selection register 3 SYSCFG_EXTISS3 Address offset 0x14 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EXTI15_SS 3 0 EXTI14_SS 3 0 EXTI13_SS 3 0 EXTI12_SS 3 0 rw rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 EX...

Page 42: ...13 pin X100 PE13 pin X101 reserved X110 reserved X111 reserved 3 0 EXTI12_SS 3 0 EXTI 12 sources selection X000 PA12 pin X001 PB12 pin X010 PC12 pin X011 PD12 pin X100 PE12 pin X101 reserved X110 reserved X111 reserved 1 6 7 System configuration register 2 SYSCFG_CFG2 Address offset 0x18 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 ...

Page 43: ...k input of TIMER0 7 19 20 1 The SRAM ECC check error is connected from the break input of TIMER0 7 19 20 0 LOCKUP_LOCK Cortex M33 LOCKUP output lock This bit is set by software and cleared by a system reset 0 The Cortex M33 LOCKUP output is disconnected from the break input of TIMER0 7 19 20 1 The Cortex M33 LOCKUP output is connected from the break input of TIMER0 7 19 20 1 6 8 System status regi...

Page 44: ... writing 1 0 no SRAM non correction event is detected 1 SRAM non correction event is detected Note SRAM two bits non correction ECC error will cause an NMI interrupt when the SRAMECCMEIE bit is set 1 6 9 System configuration register 3 SYSCFG_CFG3 Address offset 0x28 Reset value 0xXXXX X00F This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SRAMECCEADDR 13...

Page 45: ...t 0x2C Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIMER0_ETI_SEL 1 0 TIMER7_ETI_SEL 1 0 Reserved TIMER19_ETI_SEL 1 0 TIMER20_ETI_SEL 1 0 TIMER0_ BRKIN0_ SEL TIMER0_ BRKIN1_ SEL TIMER0_ BRKIN2_ SEL TIMER0_ BRKIN3_ SEL TIMER7_ BRKIN0_ SEL TIMER7_ BRKIN1_ SEL rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 T...

Page 46: ...external trigger 0 1 timer external trigger 1 10 timer external trigger 2 11 Reserved 21 TIMER0_BRKIN0_S EL TIMER0 break input 0 select 0 from GPIO pin 1 from TRIGSEL 20 TIMER0_BRKIN1_S EL TIMER0 break input 1 select 0 from GPIO pin 1 from TRIGSEL 19 TIMER0_BRKIN2_S EL TIMER0 break input 2 select 0 from GPIO pin 1 from TRIGSEL 18 TIMER0_BRKIN3_S EL TIMER0 break input 3 select 0 from GPIO pin 1 fro...

Page 47: ...MER20 break input 0 select 0 from GPIO pin 1 from TRIGSEL 4 TIMER20_BRKIN1_S EL TIMER20 break input 1 select 0 from GPIO pin 1 from TRIGSEL 3 TIMER20_BRKIN2_S EL TIMER20 break input 2 select 0 from GPIO pin 1 from TRIGSEL 2 TIMER20_BRKIN3_S EL TIMER20 break input 3 select 0 from GPIO pin 1 from TRIGSEL 1 Reserved Must be kept at reset value 0 TIMER7_CH0N_SEL TIMER7 Channel 0 complementary input se...

Page 48: ...RAM density of the device in Kbytes Example 0x0008 indicates 8 Kbytes 15 0 FLASH_DENSITY 15 0 Flash memory density The value indicates the Flash memory density of the device in Kbytes Example 0x0020 indicates 32 Kbytes 1 7 2 Unique device ID 96 bits Base address 0x1FFF F7E8 The value is factory programmed and can never be altered by user This register has to be accessed by word 32 bit 31 30 29 28 ...

Page 49: ...tions 31 0 UNIQUE_ID 63 32 Unique device ID Base address 0x1FFF F7F0 The value is factory programmed and can never be altered by user This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UNIQUE_ID 95 80 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNIQUE_ID 79 64 r Bits Fields Descriptions 31 0 UNIQUE_ID 95 64 Unique device ID ...

Page 50: ...detected 0 3 waiting time within bank0 bank1 Data Flash when CPU executes instructions and read data Pre fetch buffer to speed read operations Cache with 1K bytes which organized as 64 cache line of 2X64 bits The flash page size is 1KB Double word programming page erase and mass erase operation 1KB OTP one time program block used for user data storage 24B option bytes block for user application re...

Page 51: ...map of GD32A50x devices Information Block Bootloader 2 0x1FFF B000 0x1FFF F7FF 18KB Option byte Block Option bytes 0 0x1FFF F800 0x1FFF F817 24B Option bytes 1 0x4002 2068 4B One time program Block OTP bytes 3 0x1FFF 7000 0x1FFF 73FF 1KB Note 1 Data Flash and EEPROM backup share total 64KB Extend Flash Block It can be configured as 0 64 16 48 32 32 48 16 and 64 0 2 The Information Block stores the...

Page 52: ...igured as 0 64 16 48 32 32 48 16 and 64 0 2 The Information Block stores the boot loader This block cannot be programmed or erased by user 3 1 Kbyte 128 double word OTP one time programmable data area is for user the OTP area is only operated by bank 1 register The OTP data cannot be erased and can be written only once If any bit has been set 0 the entire double word cannot be written anymore even...

Page 53: ...ash base address and size for flash memory Block Name Address size bytes Main Flash Block bank0 Page 0 0x0800 0000 0x0800 03FF 1KB Page 1 0x0800 0400 0x0800 07FF 1KB Page 2 0x0800 0800 0x0800 0BFF 1KB Page 63 0x0800 FC00 0x0800 FFFF 1KB Extend Flash Block Data Flash 1 0x0880 0000 0x0880 3FFF 16KB EEPROM backup 1 Shared RAM EEPROM SRAM 0x08C0 0000 0x08C0 03FF 1KB Basic SRAM Refer to Table 1 2 Memor...

Page 54: ...ll be set If the ECCDETIE bit in FMC_ECCCS register is set an interrupt is generated And the data return all F When occurred in option bytes 1 the OB1ECCDET bit in FMC_ECCCS register will be set If the ECCDETIE bit in FMC_ECCCS register is set an interrupt is generated And the data return all F When occurred in other space including read option bytes 0 at 0x1FFFF80x the ECCDET bit in FMC_ECCCS reg...

Page 55: ...the AHB clock frequency is 8MHz and the WSCNT is 0 Note 1 If it is necessary to increase the AHB clock frequency firstly refer to Table 2 5 The relation between WSCNT and AHB clock frequency when LDO is 1 1V configure the WSCNT bits according to the target AHB clock frequency Then increase the AHB clock frequency to the target frequency It is forbidden to increase the AHB clock frequency before co...

Page 56: ... write RWW capability The Flash memory features a dual bank architecture based on bank 0 256 Kbytes and bank 1 up to 128 Kbytes Bootloader Data Flash EEPROM OTP Option byte This architecture supports the RWW read while write capability It means that while a read or program operation is performed in a bank the other bank can be accessed for another operation read or program without the need to wait...

Page 57: ...e erase command into PER bit in FMC_CTLx register Send the page erase command to the FMC by setting the START bit in FMC_CTLx register Wait until all the operations have been completed by checking the value of the BUSY bit in FMC_STATx register Read and verify the page if required using a DBUS access When the operation is executed successfully the ENDF in FMC_STATx register will be set An interrup...

Page 58: ...ssary Check the BUSY bit in FMC_STATx register to confirm that no flash memory operation is in progress BUSY equal to 0 Otherwise wait until the operation has been finished Write the mass erase command into MER bit in FMC_CTLx register Send the mass erase command to the FMC by setting the START bit in FMC_CTLx register Wait until all the operations have been completed by checking the value of the ...

Page 59: ...eck the WPERR bit in the FMC_STATx register to detect this condition in the interrupt handler The Figure 2 2 Process of mass erase operation indicates the mass erase operation flow Figure 2 2 Process of mass erase operation Set the MER bit Is the LK bit 0 Send the command to FMC by setting START bit Start Yes No Unlock the FMC_CTLx Is the BUSY bit 0 Yes No Is the BUSY bit 0 Yes No Finish Note The ...

Page 60: ...ation you should check the address that it has been erased If the address has not been erased PGERR bit will set when programming the address even if programming 0x0 Additionally the program operation will be ignored on protected pages Flash operation error interrupt will be triggered by the FMC if the ERRIE bit in the FMC_CTLx register is set The software can check the PGERR bit in the FMC_STATx ...

Page 61: ... the program erase operation is interrupted by a power down reset ect the contents in flash will not be guaranteed and leave in an indeterminate state So appropriate measures should be taken to avoid data loss by interrupt of program erase 2 3 9 Main Flash Fast Programming The FMC provides a fast programming function by DBUS which is used to modify the main flash memory contents A row 32 double wo...

Page 62: ...gram operation to flash 8 Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STATx register 9 Read and verify the Flash memory if required using a BUS access It is recommended to flush the cache if cache is enabled When the operation is executed successfully the ENDF in FMC_STATx register is set and an interrupt will be generated if the ENDIE bit in the F...

Page 63: ...te 1 The 32 double word must be written successively 2 The 32 double word must be aligned 3 Because the fast program do not check 0xFF in flash macro by hardware the software must check 0xFF first and don t program one row twice or more between 2 erases If program one row twice or more between 2 erases unpredictable result may occurred 4 Between setting FSTPG and START read operation is allowed bu...

Page 64: ...AT1 FMC_CTL1 FMC_ADDR1 Note It must ensure the OTP programming sequence completely without any unexpected interrupt such as system reset or power down If unexpected interrupt occurs there is very little probability of corrupt the data stored in flash memory 2 3 12 Shared RAM There are 4KB Shared RAM which can be used for basic SRAM EEPROM SRAM or fast program SRAM Basic SRAM The basic SRAM command...

Page 65: ...ured as EEPROM SRAM after system reset Note When configuring the SRAMCMD bits it is required to check which SRAM is available currently The configuration cannot be repeated For example if it is currently basic SRAM the SRAMCMD should not be configured as 10 again The current type of SRAM can be checked by BRAMRDY ERAMRDY PRAMRDY bits in FMC_WS register 2 3 13 Data Flash operation The data flash si...

Page 66: ...inate state So appropriate measures should be taken to avoid data loss by interrupt of EEPROM operation When the data flash is configured as EEPROM backup one error is detected and automatically corrected before copying data to the EEPROM SRAM If two errors are detected in EEPROM backup and the EEPROM SRAM need to load the data the data reload to the EEPROM SRAM will be all F Note 1 It is strongly...

Page 67: ...rogramming operation sequence Unlock the FMC_CTL1 register if necessary Check the BUSY bit in FMC_STAT1 register to confirm that no flash memory operation is in progress BUSY equal to 0 Otherwise wait until the operation has been finished Unlock the OBWEN bit in FMC_CTL1 register if necessary Wait until the OBWEN bit is set in the FMC_CTL1 register Write the program command into the OB0PG bit in F...

Page 68: ...D bit in FMC_CTL1 register if the LKVAL is 0x33CC the OB1LK bit in FMC_OB1CS register will be set and the option bytes 1 cannot be modified any more 4 If the unexpected value is written in option bytes 1 the PGSERR bit will be set after setting the OB1START bit and the operation will be ignored 5 To modify the EPSIZE EFALC bits the extend flash will be erased by hardware first then modify the opti...

Page 69: ...et when entering deep sleep mode 0 nWDG_HW 0 hardware free watchdog 1 software free watchdog 0x1fff f803 OB_USER_N OB_USER complement value 0x1fff f804 OB_DATA 7 0 user defined data bit 7 to 0 0x1fff f805 OB_DATA_N 7 0 OB_DATA complement value bit 7 to 0 0x1fff f806 OB_DATA 15 8 user defined data bit 15 to 8 0x1fff f807 OB_DATA_N 15 8 OB_DATA complement value bit 15 to 8 0x1fff f808 OB_BK0WP 7 0 P...

Page 70: ...acity Table 2 7 Option bytes 1 384K flash or 256K flash Address Name Description 31 16 LKVAL 15 0 Option bytes 1 Lock Value 0x33CC Lock Option bytes 1 the Option bytes 1 cannot be modified any more other value Do not lock Option bytes 1 15 EPLOAD Determines whether the flash reset sequence takes time to load the Shared RAM with valid EEPROM data 0 Shared RAM is not loaded with valid EEPROM data du...

Page 71: ...3CC Lock Option bytes 1 the Option bytes 1 cannot be modified any more other value Do not lock Option bytes 1 15 EPLOAD Determines whether the flash reset sequence takes time to load the Shared RAM with valid EEPROM data 0 Shared RAM is not loaded with valid EEPROM data during the flash reset sequence 1 Shared RAM is loaded with valid EEPROM data during the flash reset sequence 11 8 EPSIZE 3 0 Spe...

Page 72: ...ock Value 0x33CC Lock Option bytes 1 the Option bytes 1 cannot be modified any more other value Do not lock Option bytes 1 15 EPLOAD Determines whether the flash reset sequence takes time to load the Shared RAM with valid EEPROM data 0 Shared RAM is not loaded with valid EEPROM data during the flash reset sequence 1 Shared RAM is loaded with valid EEPROM data during the flash reset sequence 11 8 E...

Page 73: ...ze and partition is illegal the operation will be ignored and an error occurs If EPSIZE is 0 bytes 1111b EEPROM backup size in EFALC must be 0 If EPSIZE is not 0 bytes 1111b EEPROM backup size in EFALC must not be 0 4 It is recommended to configure the option bytes 1 only once throughout the life cycle The modification of option bytes 1 takes effect after the a system reset or setting the OBRLD bi...

Page 74: ...E 32 OB_BK0WP 30 BANK0_SIZE 32 OB_BK0WP 31 BANK0_SIZE 32 Note BANK0_SIZE is the memory size of bank0 Page erase program protection of bank 1 The page erase program protection of bank 1 can be individually enabled by configuring the OB_BK1WP 7 0 bit field to 0 in the option bytes 0 Each bit of OB_BK1WP 7 0 represents one eighth of bank 1 If a page erase operation is executed on the Option Byte regi...

Page 75: ...t for pages protected EFALC except 0x3 0xC 0xE OB_DFWP bit pages protected OB_DFWP 0 DFLASH_SIZE 8 OB_DFWP 1 DFLASH_SIZE 8 OB_DFWP 6 DFLASH_SIZE 8 OB_DFWP 7 DFLASH_SIZE 8 Table 2 13 OB_DFWP bit for pages protected EFALC 0x3 0xC 0xE OB_DFWP bit pages protected OB_DFWP 0 DFLASH_SIZE 6 OB_DFWP 1 DFLASH_SIZE 6 OB_DFWP 4 DFLASH_SIZE 6 OB_DFWP 5 DFLASH_SIZE 6 Note DFLASH_SIZE is the memory size of data ...

Page 76: ... EEPROM is forbidden If a read operation is executed to main flash in debug mode boot from SRAM or boot from boot loader mode a bus error will be generated If a program erase check blank operation is executed to main flash OTP data flash and EEPROM in debug mode boot from SRAM or boot from bootloader mode the WPERR bit in FMC_STATx register will be set At low level protection option bytes 0 block ...

Page 77: ...e 0 erase CBCMD FSTPG OB0PG MERDF MER PER PG are not cleared Set OB0ER option byte 0 program CBCMD FSTPG OB0ER MERDF MER PER PG are not cleared Set OB0PG mass erase CBCMD OB0ER OB0PG MERDF PER PG are not cleared Set MER data flash mass erase CBCMD FSTPG OB0ER OB0PG MER PER PG are not cleared No Data Flash Set MERDF page erase CBCMD FSTPG OB0ER OB0PG MERDF MER PG are not cleared FMC_ADDRx is not va...

Page 78: ...onditions Mode Condition Operation program If the program address is not erased Write data WPERR bit in FMC_CTLx register will be set if one of the conditions occurs in Table 2 18 WPERR conditions Table 2 18 WPERR conditions Mode Condition Operation program 1 The program address is write protected by option byte 2 read protection low and boot from sram or boot from bootloader or debug mode Write d...

Page 79: ...eared by configuring the SRAMCMD bits as Basic RAM or EEPROM RAM mode 0 Fast program SRAM is not ready 1 Fast program SRAM is ready 17 BRAMRDY Basic SRAM ready flag This bit is set by hardware And cleared by configuring the SRAMCMD bits as fast program RAM or EEPROM RAM mode 0 Basic SRAM is not ready 1 Basic SRAM is ready 16 ERAMRDY EEPROM SRAM ready flag This bit is set by hardware And cleared by...

Page 80: ...dress offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ECCDET ECCCOR EPECCD ET Reserved OB0ECC DET OB1ECC DET ECCDETI E ECCCOR IE OTP_EC C DF_ECC SYS_EC C BK1_EC C OB0_EC C Reserved rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rw rw r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ECCADDR 14 0 r Bits Fields Descriptions 31...

Page 81: ...detect interrupt disable 1 Two bit errors detect interrupt enable 24 ECCCORIE One bit error correct interrupt enable 0 One bit error correct interrupt disable 1 One bit error correct interrupt enable 23 OTP_ECC If an ECC bit error is detected in OTP this bit will be set And the ECCADDR records the offset address of OTP 0 No ECC error is detected in OTP 1 An ECC bit error is detected in OTP 22 DF_E...

Page 82: ...etails refer to 2 3 1 2 4 3 Unlock key register 0 FMC_KEY0 Address offset 0x08 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEY 31 16 w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 KEY 15 0 w Bits Fields Descriptions 31 0 KEY 31 0 FMC_CTL0 unlock key These bits are only be written by software Write KEY 31 0 with keys to unlock FMC...

Page 83: ...hen the operation executed successfully this bit is set by hardware The software can clear it by writing 1 4 WPERR Erase Program protection error flag bit When erase program on protected pages this bit is set by hardware The software can clear it by writing 1 3 PGAERR Program alignment error flag bit This bit is set by hardware when DBUS write data is not alignment The software can clear it by wri...

Page 84: ...rror interrupt enable bit This bit is set or clear by software0 no interrupt generated by hardware 1 error interrupt enable 9 Reserved Must be kept at reset value 8 FSTPG Main flash fast program command bit This bit is set or clear by software 0 no effect 1 main flash fast program command 7 LK FMC_CTL0 lock bit This bit is cleared by hardware when right sequence written to the FMC_KEY0 register Th...

Page 85: ... 5 4 3 2 1 0 ADDR 15 0 w Bits Fields Descriptions 31 0 ADDR 31 0 Flash erase program command address bits These bits are configured by software ADDR bits are the address of flash to be erased programmed 2 4 7 Option byte unlock key register FMC_OBKEY Address offset 0x44 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 OBKEY 31 ...

Page 86: ...8 7 6 5 4 3 2 1 0 RSTERR Reserved CBCMDE RR ENDF WPERR PGAERR PGERR PGSERR BUSY rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 RSTERR If the voltage is below 3 0V or a system reset occurs during flash programming or erasing an error will be generated and this bit will be set When the error is occurred the data in the current addre...

Page 87: ... flag bit 0 BUSY The flash is busy bit When the operation is in progress this bit is set to 1 When the operation is end or an error is generated this bit is cleared to 0 2 4 10 Control register 1 FMC_CTL1 Address offset 0x50 Reset value 0x0000 0080 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CBCMDLEN 2 0 Reserved SRAMCMD 1 0 Reserved CBCMD rw rw ...

Page 88: ...ftware 0 no interrupt generated by hardware 1 error interrupt enable 9 OBWEN Option byte erase program enable bit This bit is set by hardware when right sequence written to the FMC_OBKEY register This bit can be cleared by software 8 FSTPG Main flash fast program command bit This bit is set or clear by software 0 no effect 1 main flash fast program command 7 LK FMC_CTL1 lock bit This bit is cleare...

Page 89: ...0 PG Main flash program command bit This bit is set or clear by software 0 no effect 1 main flash program command Note This register should be reset after the corresponding flash operation completed 2 4 11 Address register 1 FMC_ADDR1 Address offset 0x54 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADDR 31 16 W 15 14 13 12 ...

Page 90: ... 19 18 17 16 DATA 15 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USER 7 0 Reserved PLEVEL 1 0 OBERR r r r Bits Fields Descriptions 31 16 DATA 15 0 Store OB_DATA 15 0 of option byte block after system reset 15 8 USER 7 0 Store OB_USER byte of option byte block after system reset 7 3 Reserved Must be kept at reset value 2 1 PLEVEL 1 0 Security Protection level 00 No protection level 01 Protect level l...

Page 91: ... 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EPWP 7 0 r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DFWP 7 0 BK1WP 7 0 r r Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 16 EPWP 7 0 Store OB_EPWP 7 0 of option bytes 0 block after system reset 15 8 DFWP 7 0 Store OB_DFWP 7 0 of option bytes 0 block after system reset 7 0 BK1WP 7 0 Store OB_BK1WP 7 0 of option bytes 0 block aft...

Page 92: ...et value 2 OB1LK When LKVAL is 0x33CC the OB1LK bit will be set If OB1LK is 1 the FMC_OB1CS register cannot be configured anymore 1 OB1STRAT Send option byte 1 change command to FMC It is set only by software and cleared when the BUSY bit is cleared 0 OB1ERR Option bytes 1 read error bit This bit is set by hardware when the option bytes 1 and its complement byte do not match and the option byte 1 ...

Page 93: ...GD32A50x User Manual 93 when the chip produced ...

Page 94: ...n in the Figure 3 1 Power supply overview The power of the VDD domain Backup domain is supplied directly by VDD An embedded LDO in the VDD VDDA domain is used to supply the 1 1V domain power 3 2 Characteristics Three power domains Backup domain VDD VDDA domain and 1 1V domain Three power saving modes Sleep Deep sleep and Standby modes Internal Voltage regulator LDO supplies around 1 1V voltage sou...

Page 95: ...et BPOR and the Backup domain software reset The BPOR signal forces the device to stay in the reset mode until VBAK is completely powered up Also the application software can trigger the Backup domain software reset by setting the BKPRST bit in the RCU_BDCTL register The clock source of the Real Time Clock RTC circuit can be derived from the Internal 40KHz RC oscillator IRC40K or the Low Speed Cry...

Page 96: ...d to operate in three different status including the Sleep mode full power on the Deep sleep mode full power on or low power and the Standby mode power off The POR PDR circuit is implemented to detect VDD VDDA and generate the power reset signal which resets the whole chip when the supply voltage is lower than the specified threshold Figure 3 2 Waveform of the POR PDR shows the relationship betwee...

Page 97: ...D threshold shows the relationship between the LVD threshold and the LVD output LVD interrupt signal depends on EXTI line 16 rising or falling edge configuration The following figure also shows the relationship between the supply voltage and the LVD signal The hysteresis voltage Vhyst is 100mV The OVD is used to detect whether the VDD VDDA supply voltage is over than a programmed threshold selecte...

Page 98: ...s VDDA can be externally connected to VDD through the external filtering circuit to avoid noise on VDDA and VSSA should be connected to VSS through the specific circuit independently Otherwise if VDDA is different from VDD VDDA must always be higher and the voltage difference should not exceed 0 3V To ensure a high accuracy on ADC and DAC the ADC DAC independent external reference voltage should b...

Page 99: ...ode Sleep mode The Sleep mode is corresponding to the SLEEPING mode of the Cortex M33 In Sleep mode only clock of Cortex M33 is off To enter the Sleep mode it is only necessary to clear the SLEEPDEEP bit in the Cortex M33 System Control Register and execute a WFI or WFE instruction If the Sleep mode is entered by executing a WFI instruction any interrupt can wake up the system If it is entered by ...

Page 100: ...leep mode is not in low driver mode by configure LDEN to 0 in the PMU_CTL0 register The low power mode enters depending on the LDOLP bit set in the PMU_CTL0 register Low driver Normal power The low driver mode in Deep sleep mode enters by configure LDEN to 1 in the PMU_CTL0 register And not in low power mode depending on the LDOLP bit reset in the PMU_CTL0 register Low driver Low power The low dri...

Page 101: ...rmal power mode normal driver mode On normal power mode or low power mode normal driver mode or low driver mode Off Configuration SLEEPDEEP 0 SLEEPDEEP 1 STBMOD 0 SLEEPDEEP 1 STBMOD 1 WURST 1 Entry WFI or WFE WFI or WFE WFI or WFE Wakeup Any interrupt for WFI Any event or interrupt when SEVONPEND is 1 for WFE Any interrupt from EXTI lines for WFI Any event or interrupt when SEVONPEND is 1 from EXT...

Page 102: ...MSW2 SRAM2 32KB 48KB power switch in deep sleep mode 0 SRAM2 power on and data retention in deep sleep mode 1 SRAM2 power off and data lost in deep sleep mode 20 SRAMSW1 SRAM1 16KB 32KB power switch in deep sleep mode 0 SRAM1 power on and data retention in deep sleep mode 1 SRAM1 power off and data lost in deep sleep mode 19 Reserved Must be kept at reset value 18 LDEN Low driver mode enable in De...

Page 103: ...set 0 No effect 1 Reset the standby flag This bit is always read as 0 2 WURST Wakeup Flag Reset 0 No effect 1 Reset the wakeup flag This bit is always read as 0 1 STBMOD Standby Mode 0 Enter the Deep sleep mode when the Cortex M33 enters SLEEPDEEP mode 1 Enter the Standby mode when the Cortex M33 enters SLEEPDEEP mode 0 LDOLP LDO Low Power Mode 0 The LDO operates normally during the Deep sleep mod...

Page 104: ...0 function If WUPEN0 is set before entering the Standby mode a rising edge on the WKUP pin0 will wake up the system from the Standby mode As the WKUP pin0 is active high the WKUP pin0 is internally configured to input pull down mode And setting this bit will trigger a wakeup event when the input is already high 7 4 Reserved Must be kept at reset value 3 OVDF Over Voltage Detector Status Flag 0 Ove...

Page 105: ... or by setting the STBRST bit in the PMU_CTL register 0 WUF Wakeup Flag 0 No wakeup event has been received 1 Wakeup event occurred from the WKUP pin or the RTC alarm event This bit is reset by the system or cleared by setting the WURST bit in the PMU_CTL register ...

Page 106: ... Characteristics 20 bytes Backup registers which can keep data under power saving mode If tamper event is detected Backup registers will be reset The active level of Tamper source PC13 can be configured RTC Clock Calibration register provides RTC alarm and second output selection and sets the calibration value Tamper control and status register BKP_TPCS can control tamper detection with interrupt ...

Page 107: ... TAMPER pin When the tamper event is detected the corresponding TEF bit in the BKP_TPCS register will be set Tamper event can generate an interrupt if tamper interrupt is enabled Any tamper event will reset all Backup data registers Note When TPAL 0 1 if the TAMPER pin is already high low before it is enabled by setting TPEN bit an extra tamper event is detected while there was no rising falling e...

Page 108: ...0 Backup data These bits are used for general purpose data storage The contents of the BKP_DATAx register will remain even if wake up action from Standby mode or system reset 4 4 2 RTC signal output control register BKP_OCTL Address offset 0x2C Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 ...

Page 109: ...libration output enable 0 Disable RTC clock calibration output 1 Enable RTC clock Calibration output When enable the TAMPER pin will output the RTC clock or RTC clock divided by 64 ASOEN has the priority over COEN When ASOEN is set the TAMPER pin will output the RTC alarm or second signal whether COEN is set or not This bit is reset only by a POR 6 0 RCCV 6 0 RTC clock calibration value The value ...

Page 110: ...CS Address offset 0x34 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TIF TEF Reserved TPIE TIR TER r r rw w w Bits Fields Descriptions 31 10 Reserved Must be kept at reset value 9 TIF Tamper interrupt flag 0 No tamper interrupt occurred 1 A tamper inter...

Page 111: ...s reset only by a system reset and wake up from Standby mode 1 TIR Tamper interrupt reset 0 No effect 1 Reset the TIF bit This bit is always read as 0 0 TER Tamper event reset 0 No effect 1 Reset the TEF bit This bit is always read as 0 ...

Page 112: ...al reset generator when exiting standby mode The power reset sets all registers to their reset values except the backup domain The power reset which active signal is low will be de asserted when the internal LDO voltage regulator is ready to provide 1 1V power for GD32A50x series The reset service routine vector is fixed at address 0x0000_0004 in the memory map System Reset A system reset is gener...

Page 113: ...OH_RSTn LOP_RSTn LOCKUP_RSTn ECC_RSTn to generate a reset LVDRSTEN LOHRSTEN LOPRSTEN LOCKUPRSTEN ECCRSTEN bit in Reset source clock register RCU_RSTSCK must be set Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset VDD power on 5 2 Clock control unit CCTL 5 2 1 Overview The clock control unit provid...

Page 114: ...ADC to ADC 15 MHz max ADC Prescaler 2 32 USARTxSEL 1 0 IRC CK_ CK_PCLK2 2 10 01 00 M 8 11 CK_CANx to CAN0 1 CANxSEL 1 0 CK_HXTAL CK_HXTAL CK_PCLK2 The frequency of AHB APB2 and the APB1 domains can be configured by each prescaler The maximum frequency of the AHB APB2 and APB1 domains is 100 MHz 100 MHz 50 MHz The Cortex System Timer SysTick external clock is clocked with the AHB clock HCLK divided...

Page 115: ...l oscillator can be switched on or off using the HXTALEN bit in the control register RCU_CTL The HXTALSTB flag in control register RCU_CTL indicates if the high speed external crystal oscillator is stable When the HXTAL is powered up it will not be released for use until this HXTALSTB bit is set by the hardware This specific delay period is known as the oscillator Start up time As the HXTAL become...

Page 116: ...operating frequency is still less accurate than HXTAL The application requirements environment and cost will determine which oscillator type is selected If the HXTAL or PLL is the system clock source to minimize the time required for the system to recover from the Deep sleep Mode the hardware forces the IRC8M clock to be the system clock when the system initially wakes up Phase Locked Loop PLL The...

Page 117: ...urce will be IRC8M and can be switched to HXTAL or PLL by changing the system clock switch bits SCS in the configuration register 0 RCU_CFG0 When the SCS value is changed the CK_SYS will continue to operate using the original clock source until the target clock source is stable When a clock source is used directly by the CK_SYS or the PLL it is not possible to stop it PLL Clock Monitor PLLM The PL...

Page 118: ...the control register RCU_CTL LCKMEN can not be enabled before LXTAL and IRC40K are enabled and ready A 4 bits plus one counter will work at IRC32K domain when LCKMEN enable If the LXTAL clock has stuck at 0 1 error or slow down about 20KHz the counter will overflow The LXTAL clock failure will been found Clock Output Capability The clock output capability is ranging from 32 kHz to 100 MHz There ar...

Page 119: ...age control The core domain voltage in Deep sleep mode can be controlled by DSLPVS 1 0 bits in the Deep sleep mode voltage register RCU_DSV Table 5 2 Core domain voltage selected in Deep sleep mode DSLPVS 1 0 Deep sleep mode voltage V 00 0 8 01 0 9 10 1 0 11 1 1 The RCU_DSV register are protected by voltage key register RCU_VKEY Only after write 0x1A2B3C4D to the RCU_VKEY register the RCU_DSV regi...

Page 120: ... flag Set by hardware to indicate if the PLL output clock is stable and ready for use 0 PLL is not stable 1 PLL is stable 24 PLLEN PLL enable Set and reset by software This bit cannot be reset if the PLL clock is used as the system clock Reset by hardware when entering Deep sleep or Standby mode 0 PLL is switched off 1 PLL is switched on 23 Reserved Must be kept at reset value 22 HXTALSCAL HXTAL f...

Page 121: ...gardless of the control bit IRC8MEN state 18 HXTALBPS External crystal oscillator HXTAL clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0 0 Disable the HXTAL bypass mode 1 Enable the HXTAL bypass mode in which the HXTAL output clock is equal to the input clock 17 HXTALSTB External crystal oscillator HXTAL clock stabilization flag Set by hardware to indicate if the H...

Page 122: ... 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PLLDV CKOUTDIV 2 0 PLLMF 4 CKOUTSEL 2 0 Reserved PLLMF 3 0 DPLL PLLSEL rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved APB2PSC 2 0 APB1PSC 2 0 AHBPSC 3 0 SCSS 1 0 SCS 1 0 rw rw rw r rw Bits Fields Descriptions 31 PLLDV The CK_PLL divide by 1 or 2 fo...

Page 123: ...urce clock x 2 00001 PLL source clock x 3 00010 PLL source clock x 4 00011 PLL source clock x 5 00100 PLL source clock x 6 00101 PLL source clock x 7 00110 PLL source clock x 8 00111 PLL source clock x 9 01000 PLL source clock x 10 01001 PLL source clock x 11 01010 PLL source clock x 12 01011 PLL source clock x 13 01100 PLL source clock x 14 01101 PLL source clock x 15 01110 PLL source clock x 16 ...

Page 124: ... 100 CK_AHB 2 selected 101 CK_AHB 4 selected 110 CK_AHB 8 selected 111 CK_AHB 16 selected 10 8 APB1PSC 2 0 APB1 prescaler selection Set and reset by software to control the APB1 clock division ratio 0xx CK_AHB selected 100 CK_AHB 2 selected 101 CK_AHB 4 selected 110 CK_AHB 8 selected 111 CK_AHB 16 selected 7 4 AHBPSC 3 0 AHB prescaler selection Set and reset by software to control the AHB clock di...

Page 125: ...000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved CKMIC PLLMIC LCKMIC PLL STBIC HXTAL STBIC IRC8M STBIC LXTAL STBIC IRC40K STBIC w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PLLMIE LCKMIE PLL STBIE HXTAL STBIE IRC8M STBIE LXTAL STBIE IRC40K STBIE CKMIF PLLMIF LCKMIF PLL STBIF HXTAL STBIF ...

Page 126: ... flag 0 Not reset IRC40KSTBIF flag 1 Reset IRC40KSTBIF flag 15 Reserved Must be kept at reset value 14 PLLMIE PLL clock monitor interrupt enable Set and reset by software to enable disable the PLL clock monitor interrupt 0 Disable the PLL clock monitor interrupt 1 Enable the PLL clock monitor interrupt 13 LCKMIE LXTAL clock monitor interrupt enable Set and reset by software to enable disable the L...

Page 127: ...NMIIE 0 Clock operating normally 1 HXTAL clock stuck 6 PLLMIF PLL clock monitor interrupt flag Set by hardware when PLL clock is stuck Reset by software when setting the PLLMIC bit 0 PLL clock operating normally 1 PLL clock stuck 5 LCKMIF LXTAL clock monitor interrupt flag Set by hardware when LXTAL clock is stuck Reset by software when setting the LCKMIC bit 0 LXTAL clock operating normally 1 LXT...

Page 128: ...z RC oscillator clock is stable and the IRC40KSTBIE bit is set Reset by software when setting the IRC40KSTBIC bit 0 No IRC40K stabilization clock ready interrupt generated 1 IRC40K stabilization interrupt generated 5 3 4 APB2 reset register RCU_APB2RST Address offset 0x0C Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23...

Page 129: ...Reset the USART0 13 TIMER7RST TIMER7 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER7 12 SPI0RST SPI0 reset This bit is set and reset by software 0 No reset 1 Reset the SPI0 11 TIMER0RST TIMER0 reset This bit is set and reset by software 0 No reset 1 Reset the TIMER0 10 ADC1RST ADC1 reset This bit is set and reset by software 0 No reset 1 Reset the ADC1 9 ADC0RST ADC0 rese...

Page 130: ...rved rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved SPI1 RST Reserved WWDGT RST Reserved TIMER6 RST TIMER5 RST Reserved TIMER1 RST rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 DACRST DAC reset This bit is set and reset by software 0 No reset 1 Reset DAC 28 PMURST Power control reset This bit is set and reset by software 0 No reset 1 ...

Page 131: ...bit is set and reset by software 0 No reset 1 Reset SPI1 13 12 Reserved Must be kept at reset value 11 WWDGTRST Window watchdog timer reset This bit is set and reset by software 0 No reset 1 Reset window watchdog timer 10 6 Reserved Must be kept at reset value 5 TIMER6RST TIMER6 timer reset This bit is set and reset by software 0 No reset 1 Reset TIMER6 timer 4 TIMER5RST TIMER5 timer reset This bi...

Page 132: ...ble This bit is set and reset by software 0 Disabled GPIO port F clock 1 Enabled GPIO port F clock 21 PEEN GPIO port E clock enable This bit is set and reset by software 0 Disabled GPIO port E clock 1 Enabled GPIO port E clock 20 PDEN GPIO port D clock enable This bit is set and reset by software 0 Disabled GPIO port D clock 1 Enabled GPIO port D clock 19 PCEN GPIO port C clock enable This bit is ...

Page 133: ...MC clock during Sleep mode 3 DMAMUXEN DMAMUX clock enable This bit is set and reset by software 0 Disabled DMAMUX clock 1 Enabled DMAMUX clock 2 SRAMSPEN SRAM interface clock enable This bit is set and reset by software to enable disable SRAM interface clock during Sleep mode 0 Disabled SRAM interface clock during sleep mode 1 Enabled SRAM interface clock during sleep mode 1 DMA1EN DMA1 clock enab...

Page 134: ...abled CAN0 clock 29 TRIGSELEN TRIGSEL clock enable This bit is set and reset by software 0 Disabled TRIGSEL clock 1 Enabled TRIGSEL clock 28 22 Reserved Must be kept at reset value 21 TIMER20EN TIMER20 timer clock enable This bit is set and reset by software 0 Disabled TIMER20 timer clock 1 Enabled TIMER20 timer clock 20 TIMER19EN TIMER19 timer clock enable This bit is set and reset by software 0 ...

Page 135: ...ace clock 8 2 Reserved Must be kept at reset value 1 CMPEN Comparator clock enable This bit is set and reset by software 0 Disabled comparator clock 1 Enabled comparator clock 0 CFGEN System configuration clock enable This bit is set and reset by software 0 Disabled system configuration clock 1 Enabled system configuration clock 5 3 8 APB1 enable register RCU_APB1EN Address offset 0x1C Reset value...

Page 136: ... interface clock 26 23 Reserved Must be kept at reset value 22 I2C1EN I2C1 clock enable This bit is set and reset by software 0 Disabled I2C1 clock 1 Enabled I2C1 clock 21 I2C0EN I2C0 clock enable This bit is set and reset by software 0 Disabled I2C0 clock 1 Enabled I2C0 clock 20 19 Reserved Must be kept at reset value 18 USART2EN USART2 clock enable This bit is set and reset by software 0 Disable...

Page 137: ...1 timer clock enable This bit is set and reset by software 0 Disabled TIMER1 timer clock 1 Enabled TIMER1 timer clock 5 3 9 Backup domain control register RCU_BDCTL Address offset 0x20 Reset value 0x0000 0018 reset by Backup domain Reset This register can be accessed by byte 8 bit half word 16 bit and word 32 bit Note The LXTALEN LXTALBPS RTCSRC and RTCEN bits of the backup domain control register...

Page 138: ...I 1 0 LXTAL drive capability Set and reset by software Backup domain reset reset this value 00 Lower driving capability 01 Medium low driving capability 10 Medium high driving capability 11 Higher driving capability reset value Note The LXTALDRI is not in bypass mode 2 LXTALBPS LXTAL bypass mode enable Set and reset by software 0 Disable the LXTAL Bypass mode 1 Enable the LXTAL Bypass mode Note In...

Page 139: ... No Low power management reset generated 1 Low power management reset generated 30 WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated Reset by writing 1 to the RSTFC bit 0 No window watchdog reset generated 1 Window watchdog reset generated 29 FWDGTRSTF Free Watchdog timer reset flag Set by hardware when a Free Watchdog timer generated Reset by ...

Page 140: ... of PLL Error reset generated Reset by writing 1 to the RSTFC bit 0 No lost of PLL error reset generated 1 Lost of PLL error reset generated 21 LOHRSTF Lost of HXTAL error reset flag Set by hardware when a Lost of HXTAL Error reset generated Reset by writing 1 to the RSTFC bit 0 No lost of HXTAL error reset generated 1 Lost of HXTAL error reset generated 20 ECCRSTF 2 bits ECC error reset flag Set ...

Page 141: ...C 2 bits error reset enable 0 No reset generated 1 ECC generates reset when ECC 2 bits error detected 11 LVDRSTEN Low voltage detection reset enable 0 No reset generated 1 Low voltage detection generates reset when Vcore is lower than pre setting 10 LOCKUPRSTEN CPU Lock Up reset enable 0 No reset generated 1 CPU Lock Up generates reset 9 2 Reserved Must be kept at reset value 1 IRC40KSTB IRC40K st...

Page 142: ...rt E reset This bit is set and reset by software 0 No reset GPIO port E 1 Reset GPIO port E 20 PDRST GPIO port D reset This bit is set and reset by software 0 No reset GPIO port D 1 Reset GPIO port D 19 PCRST GPIO port C reset This bit is set and reset by software 0 No reset GPIO port C 1 Reset GPIO port C 18 PBRST GPIO port B reset This bit is set and reset by software 0 No reset GPIO port B 1 Re...

Page 143: ...ST DMA0 reset This bit is set and reset by software 0 No reset DMA0 module 1 Reset DMA0 module 5 3 12 Configuration register 1 RCU_CFG1 Address offset 0x2C Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved PREDV 3 0 rw Bits Fields Descriptions 3...

Page 144: ...be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ADCPSC 4 0 Reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAN1SEL 1 0 CAN0SEL 1 0 Reserved USART2SEL 1 0 USART1SEL 1 0 Reserved USART0SEL 1 0 rw rw rw rw rw Bits Fields Descriptions 31 27 ADCPSC 4 0 ADC clock prescaler selection These bits are set and cleared by software Note These bits ca...

Page 145: ...ct CK_SYS 10 CK_USART1 select CK_LXTAL 11 CK_USART1 select CK_IRC8M 3 2 Reserved Must be kept at reset value 1 0 USART0SEL 1 0 CK_USART0 clock source selection This bit is set and reset by software 00 CK_USART0 select CK_HXTAL 01 CK_USART0 select CK_SYS 10 CK_USART0 select CK_LXTAL 11 CK_USART0 select CK_IRC8M 5 3 14 Voltage key register RCU_VKEY Address offset 0x100 Reset value 0x0000 0000 This r...

Page 146: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DSLPVS 1 0 rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 0 DSLPVS 1 0 Deep sleep mode voltage select These bits is set and reset by software 00 The core voltage is 0 8V in Deep sleep mode 01 The core voltage is 0 9V in Deep sleep mode 10 The core voltage is 1 0V in Deep sl...

Page 147: ...eripheral interrupts 4 bits interrupt priority configuration 16 priority levels Efficient interrupt processing Support exception pre emption and tail chaining Wake up system from power saving mode Up to 25 independent edge detectors in EXTI Three trigger types rising falling and both edges Software interrupt or event trigger Trigger sources configurable 6 3 Interrupts function overview The Arm Cor...

Page 148: ... tick timer The SysTick calibration value is 12500 and SysTick clock frequency is fixed to HCLK 0 125 So this will give a 1ms SysTick interrupt if HCLK is configured to 100MHz Table 6 2 Interrupt vector table Interrupt Number Vector Number Peripheral Interrupt Description Vector Address IRQ 0 16 Window watchdog timer interrupt 0x0000_0040 IRQ 1 17 LVD PVD through EXTI Line detection interrupt 0x00...

Page 149: ... 0x0000_00B0 IRQ 29 45 TIMER19 Break update trigger and commutation interrupt 0x0000_00B4 IRQ 30 46 TIMER19 Capture Compare interrupt 0x0000_00B8 IRQ 31 47 I2C0 event interrupt 0x0000_00BC IRQ 32 48 I2C0 error interrupt 0x0000_00C0 IRQ 33 49 I2C1 event interrupt 0x0000_00C4 IRQ 34 50 I2C1 error interrupt 0x0000_00C8 IRQ 35 51 SPI0 global interrupt 0x0000_00CC IRQ 36 52 SPI1 global interrupt 0x0000...

Page 150: ...124 IRQ58 74 DMA1 Channel 2 global interrupt 0x0000_0128 IRQ59 75 DMA1 Channel 3 global interrupt 0x0000_012C IRQ60 76 DMA1 Channel 4 global interrupt 0x0000_0130 IRQ61 77 Reserved 0x0000_0134 IRQ62 78 CAN1 wakeup through EXTI Line detection interrupt 0x0000_0138 IRQ63 79 CAN1 Interrupt for message buffer 0x0000_013C IRQ64 80 CAN1 Interrupt for Bus off Bus off done 0x0000_0140 IRQ65 81 CAN1 Interr...

Page 151: ...lines from GPIO pins and 9 lines from internal modules including LVD RTC Alarm CAN CMP USART Wakeup and Over voltage All GPIO pins can be selected as an EXTI trigger source by configuring SYSCFG_EXTISSx registers in GPIO module please refer to System configuration registers section for detail EXTI can provide not only interrupts but also event signals to the processor The Cortex M33 processor full...

Page 152: ...PA5 PB5 PC5 PD5 PE5 PF5 6 PA6 PB6 PC6 PD6 PE6 PF6 7 PA7 PB7 PC7 PD7 PE7 PF7 8 PA8 PB8 PC8 PD8 PE8 9 PA9 PB9 PC9 PD9 PE9 10 PA10 PB10 PC10 PD10 PE10 11 PA11 PB11 PC11 PD11 PE11 12 PA12 PB12 PC12 PD12 PE12 13 PA13 PB13 PC13 PD13 PE13 14 PA14 PB14 PC14 PD14 PE14 15 PA15 PB15 PC15 PD15 PE15 16 LVD 17 RTC Alarm 18 CAN0 19 CAN1 20 CMP output 21 USART0 Wakeup 22 USART1 Wakeup 23 USART2 Wakeup 24 Over vol...

Page 153: ...elds Descriptions 31 25 Reserved Must be kept at reset value 24 0 INTENx Interrupt enablebit 0 Interrupt from Linex is disabled 1 Interrupt from Linex is enabled 6 6 2 Event enable register EXTI_EVEN Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EVEN24 EVEN23 EVEN22 EVEN21 EVEN20 EVEN19 EVEN18 EV...

Page 154: ...d 1 Rising edge of Linex is valid as an interrupt event request 6 6 4 Falling edge trigger enable register EXTI_FTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved FTEN24 FTEN23 FTEN22 FTEN21 FTEN20 FTEN19 FTEN18 FTEN17 FTEN16 rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FTEN15...

Page 155: ...terrupt event request 1 Activate the EXTIx software interrupt event request 6 6 6 Pending register EXTI_PD Address offset 0x14 Reset value 0xXXXX XXXX where X is undefined This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PD24 PD23 PD22 PD21 PD20 PD19 PD18 PD17 PD16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 ...

Page 156: ...onal trigger inputs Each peripheral has its own register to select trigger input signal TRIGSEL register can be configured up to 4 outputs to peripheral Trigger input source could be external input signal or output of peripheral Trigger selection output could be for external output or peripheral 7 3 Function overview With TRIGSEL peripherals that support trigger source selection have dedicated reg...

Page 157: ...ws software to select the trigger input for peripherals The Table 7 1 Trigger input bit fields selection gives the trigger input register selection Table 7 1 Trigger input bit fields selection fields bits value trigger input selection INSELx 0x00 0 0x01 1 0x02 TRIGSEL_IN0 0x03 TRIGSEL_IN1 0x04 TRIGSEL_IN2 0x05 TRIGSEL_IN3 0x06 TRIGSEL_IN4 0x07 TRIGSEL_IN5 0x08 TRIGSEL_IN6 0x09 TRIGSEL_IN7 0x0a TRI...

Page 158: ...0x1d TIMER0_MCH3 0x1e TIMER0_TRGO 0x1f TIMER7_CH0 0x20 TIMER7_CH1 0x21 TIMER7_CH2 0x22 TIMER7_CH3 0x23 TIMER7_MCH0 0x24 TIMER7_MCH1 0x25 TIMER7_MCH2 0x26 TIMER7_MCH3 0x27 TIMER7_TRGO 0x28 TIMER19_CH0 0x29 TIMER19_CH1 0x2a TIMER19_CH2 0x2b TIMER19_CH3 0x2c TIMER19_MCH0 0x2d TIMER19_MCH1 0x2e TIMER19_MCH2 0x2f TIMER19_MCH3 0x30 TIMER19_TRGO 0x31 TIMER20_CH0 0x32 TIMER20_CH1 0x33 TIMER20_CH2 0x34 TIM...

Page 159: ... outputs which are connected to the corresponding peripherals Table 7 2 TRIGSEL input and output mapping Trigger Source Trigger select TRIGSEL Register TRIGSEL output Peripherals 1 b0 INSELx 6 0 TRIGSEL_EXOUT0 output0 output1 output2 output3 TRIGSEL_OUT0 TRIGSEL_OUT1 TRIGSEL_OUT2 TRIGSEL_OUT3 1 b1 TRIGSEL_IN0 TRIGSEL_IN1 TRIGSEL_IN2 TRIGSEL_EXOUT1 output0 output1 output2 output3 TRIGSEL_OUT4 TRIGS...

Page 160: ...MCH1 TRIGSEL_MFCOM output0 output1 output2 output3 MFCOM_TRG_TIMER0 MFCOM_TRG_TIMER1 MFCOM_TRG_TIMER2 MFCOM_TRG_TIMER3 TIMER7_MCH2 TIMER7_MCH3 TIMER7_TRGO TIMER19_CH0 TRIGSEL_CAN0 output0 CAN0_EX_TIME_TICK TIMER19_CH1 TIMER19_CH2 TIMER19_CH3 TIMER19_MCH0 TRIGSEL_CAN1 output0 output1 output2 output3 CAN1_EX_TIME_TICK TIMER19_MCH1 TIMER19_MCH2 TIMER19_MCH3 TIMER19_TRGO TRIGSEL_TIMER0IN output0 outpu...

Page 161: ...All output can select all input as trigger source except TIMERx_ITIx and TIMERx_BRKINx TIMERx_ITIx cannot select CMP_OUT and LXTAL_TRG other timers CHx MCHx signals and their own signals as trigger TIMERx_BRKINx cannot select their own signals as trigger When violate value is selected for these outputs the output will be selected as 0 When trigger input selection INSELx 6 0 bits is configured as 0...

Page 162: ...nected to output3 The output3 is used as the source of external output3 signal For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 23 Reserved Must be kept at reset value 22 16 INSEL2 6 0 Trigger input source selection for output2 These bits are used to select trigger input signal connected to output2 The output2 is used as the source of external output2 sig...

Page 163: ...onnected to output3 The output3 is used as the source of external output7 signal For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 23 Reserved Must be kept at reset value 22 16 INSEL2 6 0 Trigger input source selection for output2 These bits are used to select trigger input signal connected to output2 The output2 is used as the source of external output6 s...

Page 164: ...ster 0 TRIGSEL_ADC0 register write is enabled 1 TRIGSEL_ADC0 register write is disabled 30 7 Reserved Must be kept at reset value 6 0 INSEL0 6 0 Trigger input source selection for output0 These bits are used to select trigger input signal connected to output1 The output is used as the source of ADC0_RTTRG ADC0 routine channel group trigger input For the detailed configuration please refer to Table...

Page 165: ...value 0x0000 0015 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LK Reserved rs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INSEL0 6 0 rw Bits Fields Descriptions 31 LK TRIGSEL register lock This bit is set by software and cleared only by a system reset When it is set it disables write access to TRIGSEL_DAC register 0 TRIGSEL_DAC register write i...

Page 166: ...er input source selection for output2 These bits are used to select trigger input signal connected to output2 The output is used as the source of TIMER0_ITI2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger...

Page 167: ... bits are used to select trigger input signal connected to output2 The output is used as the source of TIMER0_BRKIN2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The ou...

Page 168: ...connected to output2 The output is used as the source of TIMER7_ITI2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of TIMER7_ITI1 trigge...

Page 169: ...t2 The output is used as the source of TIMER7_BRKIN2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of TIMER7_BRKIN1 trigger input For th...

Page 170: ...he output is used as the source of TIMER19_ITI2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of TIMER19_ITI1 trigger input For the deta...

Page 171: ...ut2 The output is used as the source of TIMER19_BRKIN2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of TIMER19_BRKIN1 trigger input For...

Page 172: ...he output is used as the source of TIMER20_ITI2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of TIMER20_ITI1 trigger input For the deta...

Page 173: ...put2 The output is used as the source of TIMER20_BRKIN2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of TIMER20_BRKIN1 trigger input Fo...

Page 174: ... as the source of TIMER1_ITI2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of TIMER1_ITI1 trigger input For the detailed configuration ...

Page 175: ..._TRG_TIMER2 trigger input For the detailed configuration please refer to Table 7 1 Trigger input bit fields selection 15 Reserved Must be kept at reset value 14 8 INSEL1 6 0 Trigger input source selection for output1 These bits are used to select trigger input signal connected to output1 The output is used as the source of MFCOM_TRG_TIMER1 trigger input For the detailed configuration please refer ...

Page 176: ...ion for CAN1 register TRIGSEL_CAN1 Address offset 0x40 Reset value 0x0000 003A This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LK Reserved rs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved INSEL0 6 0 rw Bits Fields Descriptions 31 LK TRIGSEL register lock This bit is set by software and cleared only by a system reset When it is set it disables write ...

Page 177: ...nalog mode Each GPIO pin can be configured as pull up pull down or no pull up pull down All GPIOs are high current capable except for analog mode 8 2 Characteristics Input output direction control Schmitt trigger input function enable control Each pin weak pull up pull down function Output push pull open drain enable control Output set reset control External interrupt with programmable trigger edg...

Page 178: ... down 10 AFIO INPUT X Floating 10 X 00 pull up 01 pull down 10 AFIO OUTPUT push pull Floating 10 0 00 pull up 01 pull down 10 open drain Floating 1 00 pull up 01 pull down 10 ANALOG X X 11 X XX Figure 8 1 Basic structure of a general pupose I Oshows the basic structure of an I O Port bit Figure 8 1 Basic structure of a general pupose I O Read Vss Output Control Register Write Read Write Alternate ...

Page 179: ...programming the GPIOx_OCTL at bit level the user can modify only one or several bits in a single atomic AHB write access by programming 1 to the bit operate register GPIOx_BOP or for clearing only GPIOx_BC or for toggle only GPIOx_TG The other bits will not be affected 8 3 2 External interrupt event lines All ports have external interrupt capability To use external interrupt lines the port must be...

Page 180: ...er input is enabled The weak pull up and pull down resistors could be chosen The output buffer is enabled Open Drain Mode The pad output low level when a 0 in the output control register while the pad leaves Hi Z when a 1 in the output control register Push Pull Mode The pad output low level when a 0 in the output control register while the pad output high level when a 1 in the output control regi...

Page 181: ...o suit for different device packages the GPIO supports some alternate functions mapped to some other pins by software When be configured as alternate function The output buffer is enabled in open drain or push pull configuration The output buffer is driven by the peripheral The schmitt trigger input is enabled The weak pull up and pull down resistors could be chosen The I O pin data is stored into...

Page 182: ...onfiguration to be frozen by the 32 bit locking register GPIOx_LOCK When the special LOCK sequence has occurred on LKK bit in GPIOx_LOCK register and the LKy bit is set in GPIOx_LOCK register the corresponding port is locked and the corresponding port configuration cannot be modified until the next reset It recommended to be used in the configuration of driving a power module 8 3 10 GPIO single cy...

Page 183: ...0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTL7 1 0 CTL6 1 0 CTL5 1 0 CTL4 1 0 CTL3 1 0 CTL2 1 0 CTL1 1 0 CTL0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 CTL15 1 0 Pin 15 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 29 28 CTL14 1 0 Pin 14 configuration bits These bits are set and cleared by software Refer to CTL0 1...

Page 184: ...are Refer to CTL0 1 0 description 11 10 CTL5 1 0 Pin 5 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 9 8 CTL4 1 0 Pin 4 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 7 6 CTL3 1 0 Pin 3 configuration bits These bits are set and cleared by software Refer to CTL0 1 0 description 5 4 CTL2 1 0 Pin 2 configuratio...

Page 185: ...ftware Refer to OM0 description 14 OM14 Pin 14 output mode bit These bits are set and cleared by software Refer to OM0 description 13 OM13 Pin 13 output mode bit These bits are set and cleared by software Refer to OM0 description 12 OM12 Pin 12 output mode bit These bits are set and cleared by software Refer to OM0 description 11 OM11 Pin 11 output mode bit These bits are set and cleared by softwa...

Page 186: ...tput mode bit These bits are set and cleared by software Refer to OM0 description 0 OM0 Pin 0 output mode bit These bits are set and cleared by software 0 Output push pull mode reset value 1 Output open drain mode 8 4 3 Port output speed register GPIOx_OSPD x A F Address offset 0x08 Reset value 0x000C 0000 for port B 0x0000 0000 for others This register can be accessed by byte 8 bit half word 16 b...

Page 187: ...and cleared by software Refer to OSPD0 1 0 description 19 18 OSPD9 1 0 Pin 9 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 17 16 OSPD8 1 0 Pin 8 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 description 15 14 OSPD7 1 0 Pin 7 output max speed bits These bits are set and cleared by software Refer to OSPD0 1 0 des...

Page 188: ... 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PUD15 1 0 PUD14 1 0 PUD13 1 0 PUD12 1 0 PUD11 1 0 PUD10 1 0 PUD9 1 0 PUD8 1 0 rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUD7 1 0 PUD6 1 0 PUD5 1 0 PUD4 1 0 PUD3 1 0 PUD2 1 0 PUD1 1 0 PUD0 1 0 rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 30 PUD15 1 0 Pin 15 pull up or pull down bits These bits are set and cleared by ...

Page 189: ...t and cleared by software Refer to PUD0 1 0 description 11 10 PUD5 1 0 Pin 5 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 9 8 PUD4 1 0 Pin 4 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 description 7 6 PUD3 1 0 Pin 3 pull up or pull down bits These bits are set and cleared by software Refer to PUD0 1 0 ...

Page 190: ...hese bits are set and cleared by hardware 0 Input signal low 1 Input signal high 8 4 6 Port output control register GPIOx_OCTL x A F Address offset 0x14 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OCTL15 OCTL14 OCTL13 OCTL12 OCTL11 OCTL10 OCTL9 OCT...

Page 191: ...red by software 0 No action on the corresponding OCTLy bit 1 Set the corresponding OCTLy bit 8 4 8 Port configuration lock register GPIOx_LOCK x A F Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved LKK rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LK15 LK14 LK13 LK12 LK11 LK10 LK9 LK8 LK7 LK6 LK5 LK4 LK3...

Page 192: ...e function selected These bits are set and cleared by software Refer to SEL0 3 0 description 27 24 SEL6 3 0 Pin 6 alternate function selected These bits are set and cleared by software Refer to SEL0 3 0 description 23 20 SEL5 3 0 Pin 5 alternate function selected These bits are set and cleared by software Refer to SEL0 3 0 description 19 16 SEL4 3 0 Pin 4 alternate function selected These bits are...

Page 193: ...half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SEL15 3 0 SEL14 3 0 SEL13 3 0 SEL12 3 0 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEL11 3 0 SEL10 3 0 SEL9 3 0 SEL8 3 0 rw rw rw rw Bits Fields Descriptions 31 28 SEL15 3 0 Pin 15 alternate function selected These bits are set and cleared by software Refer to SEL8 3 0 description 27 24 SEL14 3 0 Pin 14 alterna...

Page 194: ... cleared by software 0000 AF0 selected reset value 0001 AF1 selected 0010 AF2 selected 0011 AF3 selected 0100 AF4 selected 0101 AF5 selected 0110 AF6 selected 0111 AF7 selected 1000 AF8 selected 1001 AF9 selected 1010 1111 Reserved 8 4 11 Bit clear register GPIOx_BC x A F Address offset 0x28 Reset value 0x0000 0000 This register can be accessed by byte 8 bit half word 16 bit and word 32 bit 31 30 ...

Page 195: ... by byte 8 bit half word 16 bit and word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TG15 TG14 TG13 TG12 TG11 TG10 TG9 TG8 TG7 TG6 TG5 TG4 TG3 TG2 TG1 TG0 w w w w w w w w w w w w w w w w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 TGy Port toggle bit y y 0 15 These bits are set and cleared by software 0 No actio...

Page 196: ... external triggers reset enable and disable modes of highly flexible 16 bit timer Baud rate programming independent from the HCLK reprogramming Programmable logic mode by integrating external digital logic function chip or combining pin shifter timer function to produce complex output Support PWM waveform generation communication interface simulation such as UART I2C SPI I2S etc 9 3 Block diagram ...

Page 197: ...gic and registers of the MFCOM MFCOM modes MFCOM module supported two operation modes normal mode and debug mode If the MFCOM_HOLD bit in register DBG_CTL of DBG module is set the MFCOM continues to work even the Cortex M33 core halted While the MFOCM_HOLD bit is cleared the MFCOM stops in debug mode 9 4 2 Shifter Shifter is used to cache and transfer MFCOM data The TMSEL of MFCOM_SCTLx register i...

Page 198: ...An attempt to load data from an empty shifter buffer occurs buffer underrun Receive the shifter will shift data in and store data into the shifter buffer when a store event is signalled by the assigned timer data has been stored into the shifter buffer from the shifter An attempt to store data into a full shifter buffer occurs buffer overrun or when a mismatch occurs on a start stop bit check Matc...

Page 199: ...he timer mode the timer configuration register MFCOM_TMCFG should be configured Trigger configuration is a pin independent configuration that can be configured for input output data or output enable 8 bit baud counter mode The 16 bit counter is divided into two 8 bit counters lower 8 bits are used to configure the baud rate of the shift clock and when the lower 8 bits decrement to zero the timer o...

Page 200: ... the current value of the comparison register and begin to decrement according to the TMDEC 1 0 configuration 2 Based on the TMOUT 1 0 configuration the timer output is updated to its initial state The shifter controlled by this timer will not see this as the rising edge on the timer shift clock 3 As configured by SSTART 1 0 load the shift register from the shift buffer and output the first bit or...

Page 201: ...guration of TMDEC 1 0 2 The timer output clears shifters controlled by the timer which do not treat it as a falling edge on the timer shift clock but can generate a shift event if the timer shift clock will generate a shift event 3 The transmit shifters controlled by this timer will output their stop values 4 The receiving shifter controlled by this timer will store the contents of the shift regis...

Page 202: ...r to a shifter This process is synchronized with the MFCOM clock so there is a 1 cycle delay So when using a pin input as a timer trigger timer clock or shifter data input a synchronization delay occurs external pin 0 5 to 1 5 MFCOM clock cycles and Internal drive pin for one MFCOM clock cycle Specific application for timing considerations output valid time and input setting time you can refer to ...

Page 203: ...eam When a byte is written to SBUFx to support LSB leaving the rest of the data frame unchanged additional stop bits and idle frames are inserted UART transmit configuration 1 Set the bits SSTOP 1 0 and SSART 1 0 as 0b11 and 0b10 in register MFCOM_SCFGx respectively and set the start bit to 0 and the stop bit to 1 2 Set the bits SPCFG 1 0 and SMOD 1 0 as 0b11 and 0b010 in register MFCOM_SCTLx resp...

Page 204: ...0 Can invert input data by setting PINPL 3 Set the bit TMCVALUE 15 0 as 0x0F01 in register MFCOM_TMCMPx configure 8 bit transfer with baud rate of divide by 4 of the MFCOM clock Set TMCVALUE 15 8 number of bits x 2 1 Set TMCVALUE 7 0 baud rate divider 2 1 4 Set the bits TMOUT 1 0 TMDEC 1 0 TMRST 2 0 TMSTOP 1 0 TMDIS 2 0 TMEN 2 0 and TMSTART as 0b10 0b00 0b100 0b10 0b010 0b100 and 0b1 in register M...

Page 205: ...pin 1 Trigger is internal using shifter 0 flag 9 Set the bit SBUF 31 0 as data to receive in register MFCOM_SBUFx received data can be read from SBUFBYS 7 0 use the shifter status flag to indicate when data can be read using interrupt or DMA request Can support MSB first transfer by reading from SBUFBIS 7 0 register instead SPI master The SPI main mode uses two timers two shifters and four pins Ei...

Page 206: ... register MFCOM_SBUFx transmit data can be written to MFCOM_SBUFx use the shifter status flag to indicate when data can be written using interrupt or DMA request Can support MSB first transfer by writing to MFCOM_SBUFBBSx register instead 12 Set the bit SBUF 31 0 as data to receive in register MFCOM_SBUF x 1 received data can be read from MFCOM_SBUFBYSx use the sifter status fag to indicate when d...

Page 207: ...ead using interrupt or DMA request Can support MSB first transfer by reading from MFCOM_SBUFBISx register instead SPI slave SPI slave mode using one timer two converters and four pins Support CPHA 0 or CPHA 1 using DMA multiple transfers For CPHA 1 the clock can be kept high in multiple transmissions and the timer status flag can be used to determine the end of transmission Before the external sla...

Page 208: ...as 0b1 0b001 and 0b001 in register MFCOM_SCTL x 1 respectively configure receive using timer 0 on rising edge of shift clock with input data on pin 1 5 Set the value of register MFCOM_TMCMPx as 0x0000003F configure 32 bit transfer Set TMCVALUE 15 0 number of bits x 2 1 6 Set the bits TMOUT 1 0 TMDEC 1 0 TMDIS 2 0 TMEN 2 0 and TMSTART as 0b01 0b10 0b110 0b110 and 0b1 in register MFCOM_TMCFGx respec...

Page 209: ...the next rising edge on the SCL and then disable both timers The transmitter shifter should be disabled after waiting for a set delay in a repetitive start or stop condition The sending output data is valid for 3 MFCOM_CLK cycles and due to synchronization delays the maximum baud rate is the MFCOM clock frequency divided by 8 Before the transmitter receiver shifter starts timing the clock output w...

Page 210: ...SBUF x 1 received data can be read from SBUFBIS 7 0 use the shifter status flag to indicate when data can be read using interrupt or DMA request I2S master The I2S master mode uses two timers two shifters and four pins One timer is used to generate the bit clock and control the shifter and the other is used to generate frame synchronization Supports DMA data transfer The shift error flag will be s...

Page 211: ...it data can be written to MFCOM_SBUFBISx use the shifter status flag to indicate when data can be written using interrupt or DMA request Can support LSB first transfer by writing to MFCOM_SBUF register instead 12 Set the bit SBUF 31 0 as data to receive in register MFCOM_SBUF x 1 received data can be read from MFCOM_SBUFBISx use the shifter status flag to indicate when data can be read using inter...

Page 212: ...vely configure enable on pin bit clock rising edge with trigger timer 0 high and disable on compare initial clock state is logic 1 and decrement on pin input bit clock 10 Set the bits TRIGSEL 3 0 TRIGSRC TMPSEL 2 0 TMPPL and TMMOD 1 0 as 0b0011 0b1 0b010 0b1 and 0b11 in register MFCOM_TMCTL x 1 respectively configure 16 bit counter using inverted pin 2 input bit clock with timer 0 output as the tr...

Page 213: ...kept at reset value 1 SWRSTEN Software reset enable register accesses are ignored except the control register until this bit is cleared 0 disable software reset 1 enable software reset all MFCOM registers except the control register are reset 0 MFCOMEN MFCOM enable 0 Disable MFCOM module 1 Enable MFCOM module 9 5 2 Pin data register MFCOM_PINDATA Address offset 0x04 Reset value 0x0000 0000 This re...

Page 214: ...e shifter and cleared when the MFCOM_SBUF register is read SMOD Transmit the status flag is set when MFCOM_SBUF data is transferred to the shifter or initially configured for this mode and cleared when data is written to the MFCOM_SBUF register SMOD match store when a match occurs between MFCOM_SBUF and the shifter the status flag is set and when the MFCOM_SBUF register is read the status flag is ...

Page 215: ... the SHIFTBUF register can also clear the flag bits 0 Shifter x error flag is not set 1 Shifter x error flag is set 9 5 5 Timer status register MFCOM_TMSTAT Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TMSTAT 3 0 w1c Bits Fields Descriptions 31 4 Re...

Page 216: ...lds Descriptions 31 4 Reserved Must be kept at reset value 3 0 SSIEN 3 0 Shifter status interrupt enable Enable interrupt when the shifter x status flags in bit field SSTAT 3 0 are set 0 Shifter status flags do not generate interrupts 1 Shifter status flags generate interrupts 9 5 7 Shifter error interrupt enable register MFCOM_SEIEN Address offset 0x1C Reset value 0x0000 0000 This register has to...

Page 217: ...e interrupt when timer x status flags in bit field TMSTAT 3 0 are set 0 Timer status flags do not generate interrupts 1 Timer status flags generate interrupts 9 5 9 Shifter status DMA enable register MFCOM_SSDMAEN Address offset 0x28 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 218: ...e shift clock and control the shift logic 00 Select timer 0 01 Select timer 1 10 Select timer 2 11 Select timer 3 23 TMPL Timer polarity 0 Shift on rising edge of shift clock 1 Shift on falling edge of shift clock 22 18 Reserved Must be kept at reset value 17 16 SPCFG 1 0 Shifter pin configuration 00 Shifter pin input 01 Shifter pin open drain 10 Shifter cascade pin input output data 11 Shifter pi...

Page 219: ...value 8 INSRC Input source Selects the input source for the shifter 0 Pin 1 Output of shifter x 1 x 3 7 6 Reserved Must be kept at reset value 5 4 SSTOP 1 0 Shifter stop bit 00 Disable stop bit 01 Reserved 10 In transmit mode the stop bit is valid at low level In receive or match store mode the stop bit is not low level 11 In transmit mode stop bit high is valid In receive or match store mode stop...

Page 220: ... bit 9 5 12 Shifter buffer x register MFCOM_SBUFx Address offset 0x200 0x004 x x 0 to 3 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SBUF 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SBUF 15 0 rw Bits Fields Descriptions 31 0 SBUF 31 0 Shift buffer Based on SMOD settings shift buffer data can be used for the following fun...

Page 221: ...0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SBUFBYS 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SBUFBYS 15 0 rw Bits Fields Descriptions 31 0 SBUFBYS 31 0 Shift buffer byte swapped Same as the MFCOM_SBUF register except that the read write register is byte swapped and reads return SBUF 7 0 SBUF 15 8 SBUF 23 16 SBUF 31 24 9 5 15 Shi...

Page 222: ...served TRIGSEL 3 0 TRIGPL TRIGSRC Reserved TMPCFG 1 0 rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TMPSEL 2 0 TMPPL Reserved TMMOD 1 0 rw rw rw Bits Fields Descriptions 31 28 Reserved Must be kept at reset value 27 24 TRIGSEL 3 0 Trigger select Select external trigger TRIGSRC 0 0001 external trigger 0 input 0010 external trigger 1 input 0100 external trigger 2 input 1000 external tri...

Page 223: ...et value 10 8 TMPSEL 2 0 Timer Pin Select Select the pin to use for the timer input or output 7 TMPPL Timer Pin Polarity Configures pins as an output 0 Pin active high 1 Pin active low 6 2 Reserved Must be kept at reset value 1 0 TMMOD 1 0 Timer Mode 00 Disable timer 01 Dual 8 bit counters baud mode 10 Dual 8 bit counters PWM high mode 11 Single 16 bit counter mode 9 5 17 Timer configuration x reg...

Page 224: ...r on trigger input shift clock equal to timer output 10 Decrement counter on pin input shift clock equal to pin input 11 Decrement counter on trigger input shift clock equal to trigger input 19 Reserved Must be kept at reset value 18 16 TMRST 2 0 Timer reset Configure the condition that causes the timer counter and the timer output to be reset Note In 8 bit counter mode the timer reset will only r...

Page 225: ...ng edge 111 Enabled on trigger rising or falling edge 7 6 Reserved Must be kept at reset value 5 4 TMSTOP 1 0 Timer stop bit 00 Disable stop bit 01 Enable stop bit on timer compare 10 Enable stop bit on timer disable 11 Enable stop bit on timer compare and timer disable 3 2 Reserved Must be kept at reset value 1 TMSTART Timer start bit 0 Disable start bit 1 Enabled start bit 0 Reserved Must be kep...

Page 226: ...ter mode lower 8 bits configure the baud rate divider TMCVALUE 7 0 1 2 upper 8 bits configure the number of bits in each word TMCVALUE 15 8 1 2 8 bit PWM high mode lower 8 bits configure the high period of the output to TMCVALUE 7 0 1 upper 8 bits configure the low period of the output to TMCVALUE 15 8 1 16 bit counter mode baud rate divider TMCVALUE 15 0 1 2 When the shift clock source is a pin o...

Page 227: ...s 7 8 16 32 bit data input For 7 8 16 32 bit input data length the calculation cycles are 1 2 4 AHB clock cycles User configurable polynomial value and size After CRC module reset user can configure initial value Free 8 bit register is unrelated to calculation and can be used for any other goals by any other peripheral devices Figure 10 1 Block diagram of CRC calculation unit AHB BUS Interface Inp...

Page 228: ...ata is 0x1A2B3C4D 1 byte reverse 32 bit data is divided into 4 groups and reverse implement in group inside Reversed data 0x58D43CB2 2 half word reverse 32 bit data is divided into 2 groups and reverse implement in group inside Reversed data 0xD458B23C 3 word reverse 32 bit data is divided into 1 groups and reverse implement in group inside Reversed data 0xB23CD458 For output data reverse type is ...

Page 229: ...used to calculate new data and the register can be written the new data directly Write value cannot be read because the read value is the previous CRC calculation result 10 4 2 Free data register CRC_FDATA Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserve...

Page 230: ...1 0 Reverse type for input data 0 Dot not use reverse for input data 1 Reverse input data with every 8 bit length 2 Reverse input data with every 16 bit length 3 Reverse input data with whole 32 bit length 4 3 PS 1 0 Size of polynomial 0 32 bit 1 16 bit POLY 15 0 is used for calculation 2 8 bit POLY 7 0 is used for calculation 3 7 bit POLY 6 0 is used for calculation 2 1 Reserved Must be kept at r...

Page 231: ... CRC data value When RST bit in CRC_CTL asserted CRC_DATA will be programmed to this value 10 4 5 Polynomial register CRC_POLY Address offset 0x14 Reset value 0x04C1 1DB7 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POLY 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POLY 15 0 rw Bits Fields Descriptions 31 0 POLY 31 0 User configurable polynomial...

Page 232: ...e CPU access to the system bus for some bus cycles Round robin scheduling is implemented in the bus matrix to ensure at least half of the system bus bandwidth for the CPU 11 2 Characteristics Programmable length of data to be transferred max to 65536 12 channels 7 for DMA0 and 5 for DMA1 and each channel are configurable AHB and APB peripherals FLASH SRAM can be accessed as source and destination ...

Page 233: ...peripheral requests coming at the same time Channel management to control address data selection and data counting 11 4 Function overview 11 4 1 DMA operation Each DMA transfer consists of two operations including the loading of data from the source and the storage of the loaded data to the destination The source and destination addresses are computed by the DMA controller based on the programmed ...

Page 234: ...0 0x4 4 Read B7B6 15 0 0x6 1 Write 0000B1B0 31 0 0x0 2 Write 0000B3B2 31 0 0x4 3 Write 0000B5B4 31 0 0x8 4 Write 0000B7B6 31 0 0xC 16 bits 16 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 Read B7B6 15 0 0x6 1 Write B1B0 15 0 0x0 2 Write B3B2 15 0 0x2 3 Write B5B4 15 0 0x4 4 Write B7B6 15 0 0x6 16 bits 8 bits 1 Read B1B0 15 0 0x0 2 Read B3B2 15 0 0x2 3 Read B5B4 15 0 0x4 4 R...

Page 235: ...d peripherals including a request signal and an acknowledge signal Request signal asserted by peripheral to DMA controller indicating that the peripheral is ready to transmit or receive data Acknowledge signal responded by DMA to peripheral indicating that the DMA controller has initiated an AHB command to access the peripheral Figure 11 2 Handshake mechanism shows how the handshake mechanism work...

Page 236: ... implemented to handle continue peripheral requests for example ADC scan mode The circular mode is enabled by setting the CMEN bit in the DMA_CHxCTL register In circular mode the CNT bits are automatically reloaded with the pre programmed value and the full transfer finish flag is asserted at the end of every DMA transfer DMA can always responds the peripheral request until the CHEN bit in the DMA...

Page 237: ...er to enable the channel 11 4 8 Interrupt Each DMA channel has a dedicated interrupt There are three types of interrupt event including full transfer finish half transfer finish and transfer error Each interrupt event has a dedicated flag bit in the DMA_INTF register a dedicated clear bit in the DMA_INTC register and a dedicated enable bit in the DMA_CHxCTL register The relationship is described i...

Page 238: ...38 11 4 9 DMA request mapping The DMA requests of a channel are coming from the AHB APB peripherals through the corresponding channel output of DMAMUX request multiplexer refer to Table 12 3 Request multiplexer input mapping ...

Page 239: ... Must be kept at reset value 27 23 19 15 11 7 3 ERRIFx Error flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Transfer error has not occurred on channel x 1 Transfer error has occurred on channel x 26 22 18 14 10 6 2 HTFIFx Half transfer finish flag of channel x x 0 6 Hardware set and software cleared by configuring DMA_INTC register 0 Half number of tra...

Page 240: ...el x x 0 6 0 No effect 1 Clear error flag 26 22 18 14 10 6 2 HTFIFCx Clear bit for half transfer finish flag of channel x x 0 6 0 No effect 1 Clear half transfer finish flag 25 21 17 13 9 5 1 FTFIFCx Clear bit for full transfer finish flag of channel x x 0 6 0 No effect 1 Clear full transfer finish flag 24 20 16 12 8 4 0 GIFCx Clear global interrupt flag of channel x x 0 6 0 No effect 1 Clear GIFx...

Page 241: ...et and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 9 8 PWIDTH 1 0 Transfer data size of peripheral Software set and cleared 00 8 bit 01 16 bit 10 32 bit 11 Reserved These bits can not be written when CHEN is 1 7 MNAGA Next address generation algorithm of memory Software set and cleared 0 Fixed address mode 1 Increasing address mode This bit can not...

Page 242: ...leared 0 Disable channel half transfer finish interrupt 1 Enable channel half transfer finish interrupt 1 FTFIE Enable bit for channel full transfer finish interrupt Software set and cleared 0 Disable channel full transfer finish interrupt 1 Enable channel full transfer finish interrupt 0 CHEN Channel enable Software set and cleared 0 Disable channel 1 Enable channel 11 5 4 Channel x counter regis...

Page 243: ...t value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PADDR 31 16 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PADDR 15 0 rw Bits Fields Descriptions 31 0 PADDR 31 0 Peripheral base address These bits can not be written when CHEN in the DMA_CHxCTL register is 1 When PWIDTH is 01 16 bit the LSB of these bits is ignored Access is automaticall...

Page 244: ...en CHEN in the DMA_CHxCTL register is 1 When MWIDTH in the DMA_CHxCTL register is 01 16 bit the LSB of these bits is ignored Access is automatically aligned to a half word address When MWIDTH in the DMA_CHxCTL register is 10 32 bit the two LSBs of these bits are ignored Access is automatically aligned to a word address ...

Page 245: ... pending until it is served by the DMA controller which generates a DMA acknowledge signal the DMA request signal is de asserted 12 2 Characteristics 12 channels for DMAMUX request multiplexer 4 channels for DMAMUX request generator Support 27 trigger inputs Support 27 synchronization inputs Each DMAMUX request generator channel DMA request trigger input selector DMAMUX request generator counter T...

Page 246: ...C To DMA controller Reqx_out Counter underrun Evtx_out Synchronization inputs Syncx_in Configuration Register 12 4 Function overview As shown in Figure 12 1 Block diagram of DMAMUX DMAMUX includes two sub blocks DMAMUX request multiplexer DMAMUX request multiplexer inputs Reqx_in source from Peripherals Peri_reqx DMAMUX request generator outputs Gen_reqx DMAMUX request multiplexer outputs Reqx_out...

Page 247: ... unit of request multiplexer channels And there is a built in DMAMUX request multiplexer counter for each request multiplexer channel Request multiplexer channel A DMA request input for the DMAMUX request multiplexer channel x is configured by the MUXID 6 0 bits in the DMAMUX_RM_CHxCFG register sourced either from the peripherals or from the DMAMUX request generator the sources can refer to Table ...

Page 248: ...0 bits of the DMAMUX_RM_CHxCFG register The number of DMA requests transferred to the request multiplexer channel x output following a detected synchronization event is NBR 4 0 1 Figure 12 2 Synchronization mode shows an example when NBR 4 0 4 SYNCEN 1 EVGEN 1 SYNCP 1 0 01 Figure 12 2 Synchronization mode The selected Reqx_in Syncx_in Evtx_out 4 3 2 1 Reqx_out 0 DMAMUX request multiplexer counter ...

Page 249: ...BR 4 0 4 SYNCEN 0 EVGEN 1 Figure 12 3 Event generation The selected Reqx_in Reqx_out Evtx_out 4 3 2 1 SYNCEN DMAMUX request multiplexer counter Pending DMA request 4 3 2 0 4 3 1 0 1 2 0 EVGEN Counter underrun event occurs Note If EVGEN 1 and NBR 4 0 0 an event is generated after each served DMA request Synchronization overrun If a new synchronization event occurs before the built in DMAMUX request...

Page 250: ...t generator channel is decremented At the request generator counter underrun the request generator channel stops generating DMA requests The built in DMAMUX request generator counter will be automatically reloaded to its programmed value upon the next trigger input event the built in counter is programmed by the NBRG 4 0 bits of the DMAMUX_RG_CHxCFG register Note The number of generated DMA reques...

Page 251: ...channel y TOIFy TOIFCy TOIE Trigger overrun interrupt When the DMAMUX request trigger overrun flag TOIFx is set and the trigger overrun interrupt is enabled by setting TOIE bit a trigger overrun interrupt will be generated The overrun flag TOIFx is reset by writing 1 to the corresponding clear bit of overrun flag TOIFCx in the DMAMUX_RG_INTC register Synchronization overrun interrupt When the sync...

Page 252: ... I2C1_RX 9 I2C1_TX 10 I2C0_RX 11 I2C0_TX 12 MFCOM_SSTAT0 13 MFCOM_SSTAT1 14 MFCOM_SSTAT2 15 MFCOM_SSTAT3 16 SPI0_RX 17 SPI0_TX 18 SPI1_RX 19 SPI1_TX 20 TIMER0_CH0 21 TIMER0_CH1 22 TIMER0_CH2 23 TIMER0_CH3 24 TIMER0_TI 25 TIMER0_UP 26 TIMER0_CO 27 TIMER0_MCH0 28 TIMER0_MCH1 29 TIMER0_MCH2 30 TIMER0_MCH3 31 TIMER1_CH0 32 TIMER1_CH1 33 TIMER1_CH2 34 TIMER1_CH3 35 TIMER1_TI 36 TIMER1_UP 37 TIMER7_CH0 ...

Page 253: ...48 CAN1 49 CAN0 50 USART0_RX 51 USART0_TX 52 USART1_RX 53 USART1_TX 54 USART2_RX 55 USART2_TX 56 TIMER5_UP 57 TIMER6_UP 58 TIMER19_CH0 59 TIMER19_CH1 60 TIMER19_CH2 61 TIMER19_CH3 62 TIMER19_TI 63 TIMER19_UP 64 TIMER19_CO 65 TIMER19_MCH0 66 TIMER19_MCH1 67 TIMER19_MCH2 68 TIMER19_MCH3 69 TIMER20_CH0 70 TIMER20_CH1 71 TIMER20_CH2 72 TIMER20_CH3 73 TIMER20_TI 74 TIMER20_UP 75 TIMER20_CO 76 TIMER20_M...

Page 254: ... DMAMUX_RG_CHxCFG register the sources can refer to Table 12 4 Trigger input mapping Table 12 4 Trigger input mapping Trigger input identification TID 4 0 Source 0 EXTI_0 1 EXTI_1 2 EXTI_2 3 EXTI_3 4 EXTI_4 5 EXTI_5 6 EXTI_6 7 EXTI_7 8 EXTI_8 9 EXTI_9 10 EXTI_10 11 EXTI_11 12 EXTI_12 13 EXTI_13 14 EXTI_14 15 EXTI_15 16 Evtx_out0 17 Evtx_out1 18 Evtx_out2 19 Evtx_out3 20 Reserved 21 Reserved 22 TIM...

Page 255: ...t mapping Table 12 5 Synchronization input mapping Synchronization input identification SYNCID 4 0 Source 0 EXTI_0 1 EXTI_1 2 EXTI_2 3 EXTI_3 4 EXTI_4 5 EXTI_5 6 EXTI_6 7 EXTI_7 8 EXTI_8 9 EXTI_9 10 EXTI_10 11 EXTI_11 12 EXTI_12 13 EXTI_13 14 EXTI_14 15 EXTI_15 16 Evtx_out0 17 Evtx_out1 18 Evtx_out2 19 Evtx_out3 20 Reserved 21 Reserved 22 TIMER20_CH0_O 23 Reserved 24 Reserved 25 Reserved 26 Reserv...

Page 256: ...Reserved Must be kept at reset value 28 24 SYNCID 4 0 Synchronization input identification Selects the synchronization input source 23 19 NBR 4 0 Number of DMA requests to forward The number of DMA requests to forward to the DMA controller after a synchronization event before an output event is generated equals to NBR 4 0 1 These bits shall only be written when both SYNCEN and EVGEN bits are disab...

Page 257: ...F3 SOIF2 SOIF1 SOIF0 r r r r r r r r r r r r Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 SOIFx Synchronization overrun event flag of request multiplexer channel x x 0 11 The flag is set when a synchronization event occurs on a DMA request line multiplexer channel x while the DMA request counter value is lower than NBR 4 0 The flag is cleared by writing 1 to the corresp...

Page 258: ... 18 17 16 Reserved NBRG 4 0 RGTP 1 0 RGEN rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved TOIE Reserved TID 4 0 rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 19 NBRG 4 0 Number of DMA requests to be generated The number of DMA requests to be generated after a trigger event equals to NBRG 4 0 1 Note These bits shall only be written when RGEN bit is disabled 18...

Page 259: ... kept at reset value 3 0 TOIFx Trigger overrun event flag of request generator channel x x 0 3 The flag is set when a new trigger event occurs on DMA request generator channel x before the request counter underrun the internal request counter programmed via the NBRG 4 0 bits of the DMAMUX_RG_CHxCFG register The flag is cleared by writing 1 to the corresponding TOIFCx bit in the DMAMUX_RG_INTC regi...

Page 260: ...31 4 Reserved Must be kept at reset value 3 0 TOIFCx Clear bit for trigger overrun event flag of request generator channel x x 0 3 Writing 1 in each bit clears the corresponding overrun flag TOIFx in the DMAMUX_RG_INTF register ...

Page 261: ...view Debug capabilities can be accessed by a debug tool via serial wire SW Debug Port or JTAG interface JTAG Debug Port 13 2 1 Switch JTAG or SW interface By default the JTAG interface is active The sequence for switching from JTAG to SWD is Send 50 or more TCK cycles with TMS 1 Send the 16 bit sequence on TMS 1110011110011110 0xE79E LSB first Send 50 or more TCK cycles with TMS 1 The sequence for...

Page 262: ...JTAG Because of the data shift under BSD JTAG BYPASS mode adding 1 extra bit to the data chain is needed The BSD JTAG IDCODE is 0x06418041 13 2 4 Debug reset The JTAG DP and SW DP registers are in the power on reset domain The system reset initializes the majority of the Cortex M33 excluding NVIC and debug logic FPB DWT and ITM The NJTRST reset can reset JTAG TAP controller only So it can perform ...

Page 263: ... mode the clock of AHB bus for CPU is not closed and the debugger can debug in sleep mode 13 3 2 Debug support for TIMER I2C WWDGT and FWDGT When the core halted and the corresponding bit in DBG control register DBG_CTL is set the following behaved For TIMER the timer counters stopped and hold for debug For I2C SMBUS timeout hold for debug For WWDGT or FWDGT the counter clock stopped for debug For...

Page 264: ...0000 0000 power reset only This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TIMER19 _HOLD TIMER20 _HOLD Reserved CAN1_HO LD CAN0_HO LD MFCOM_ HOLD TIMER6_ HOLD TIMER5_ HOLD Reserved TIMER7_ HOLD I2C1_HO LD rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I2C0_HO LD Reserved TIMER1_ HOLD TIMER0_ HOLD WWDGT _HOLD FWDGT_ HOLD Reserved STB...

Page 265: ...t by software 0 no effect 1 Hold the TIMER6 counter for debug when core halted 19 TIMER5_HOLD TIMER5 hold bit This bit is set and reset by software 0 no effect 1 Hold the TIMER5 counter for debug when core halted 18 Reserved Must be kept at reset value 17 TIMER7_HOLD TIMER7 hold bit This bit is set and reset by software 0 no effect 1 Hold the TIMER7 counter for debug when core halted 16 I2C1_HOLD ...

Page 266: ... the FWDGT counter clock for debug when core halted 7 3 Reserved Must be kept at reset value 2 STB_HOLD Standby mode hold register This bit is set and reset by software 0 no effect 1 At the standby mode the clock of AHB bus and system clock are provided by CK_IRC8M Configured by software a system reset generated when exit standby mode 1 DSLP_HOLD Deep sleep mode hold register This bit is set and r...

Page 267: ... bit 8 bit or 6 bit Foreground calibration function Programmable sampling time Data storage mode the most significant bit and the least significant bit DMA support Analog input channels 16 external analog inputs 1 channel for internal temperature sensor VSENSE 1 channel for internal reference voltage VREFINT Start of conversion can be initiated By software By TRIGSEL Operation modes Converts a sin...

Page 268: ...pin description Table 14 1 ADC internal input signals Internal signal name Description VSENSE Internal temperature sensor output voltage VREFINT Internal voltage reference output voltage Table 14 2 ADC input pins definition Name Remarks VDDA Analog power supply equals to VDD and 2 7 V VDDA 5V VSSA Ground for analog power supply equals to VSS VREF The positive reference voltage for the ADC 2 7 V VR...

Page 269: ...ich is internally applied to the ADC until the next ADC power off The application must not use the ADC during calibration and must wait until it is completed Calibration should be performed before starting A D conversion The calibration is initiated by software by setting bit CLB 1 CLB bit stays at 1 during all the calibration sequence It is then cleared by hardware as soon as the calibration is c...

Page 270: ...SQ0 ADC_RSQ2 registers specify the selected channels of the routine sequence The RL 3 0 bits in the ADC_RSQ0 register specify the total conversion sequence length 14 4 5 Operation modes Single operation mode In the single operation mode the ADC performs conversion on the channel specified in the RSQ0 4 0 bits of ADC_RSQ2 at a routine trigger When the ADCON has been set high the ADC samples and con...

Page 271: ...Q0 with the analog channel number 3 Configure ADC_SAMPTx register 4 Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need 5 Set the SWRCST bit or generate a TRIGSEL trigger for the routine sequence 6 Wait the EOC flag to be set 7 Read the converted date in the ADC_RDATA register 8 Clear the EOC flag by writing 0 to it 9 Repeat steps 6 8 as soon as the conversion is in need To get rid ...

Page 272: ...TL1 register if in need 4 Prepare the DMA module to transfer data from the ADC_RDATA 5 Set the SWRCST bit or generate a TRIGSEL trigger for the routine sequence 6 Wait the EOC flag to be set 7 Clear the EOC flag by writing 0 to it Figure 14 5 Scan operation mode continuous enable CH2 CH1 CH5 CH7 CH11 CH2 CH1 EOC One circle of routine sequence RL 4 Routine trigger CH5 CH7 CH11 CH2 Discontinuous ope...

Page 273: ...the ADC_CTL0 register is set routine sequence When the analog voltage converted by the ADC is below a low threshold or above a high threshold the WDE0 bit in ADC_STAT register will be set An interrupt will be generated if the WDE0IE bit is set The ADC_WDHT0 and ADC_WDLT0 registers are used to specify the high and low threshold The comparison is done before the alignment so the threshold value is i...

Page 274: ...an be specified by the SPTn 2 0 bits in the ADC_SAMPT0 and ADC_SAMPT1 registers A different sample time can be specified for each channel For 12 bits resolution the total conversion time is sampling time 12 5 CK_ADC cycles Example CK_ADC 15MHz and sample time is 2 5 cycles the total conversion time is 2 5 12 5 CK_ADC cycles that means 1us 14 4 9 External trigger configuration The conversion of rou...

Page 275: ...sensor 1 Configure the ADC clock not greater than 5MHz 2 Configure the conversion sequence ADC_IN16 and the sampling time ts_temp μs for the channel 3 Enable the temperature sensor by setting the TSVEN bit in the ADC control register 1 ADC_CTL1 4 Start the ADC conversion by setting the ADCON bit or by trigger 5 Read the resulting temperature data Vtemperature in the ADC data register and get the t...

Page 276: ...MHz 12 12 5 833 ns 2 5 15 1000 ns 10 10 5 700 ns 2 5 13 867 ns 8 8 5 567ns 2 5 11 733 ns 6 6 5 433 ns 2 5 9 600 ns 14 4 13 On chip hardware oversampling The on chip hardware oversampling circuit performs data preprocessing to offload the CPU It can handle multiple conversions and average them into a single data with increased data width up to 16 bit The on chip hardware oversampling circuit is ena...

Page 277: ...indicates truncation below gives the data format for the various N and M combination for a raw conversion data equal to 0xFFF Table 14 5 Maximum output results for N and M combimations grayed values indicates truncation Oversa mpling ratio Max Raw data No shift OVSS 0000 1 bit shift OVSS 0001 2 bit shift OVSS 0010 3 bit shift OVSS 0011 4 bit shift OVSS 0100 5 bit shift OVSS 0101 6 bit shift OVSS 0...

Page 278: ...ent delay equal to N tADC N tSMPL tCONV 14 2 14 5 ADC sync mode In devices with more than one ADC the ADC sync mode can be used In ADC sync mode the conversion starts alternately or simultaneously triggered by ADC0 to ADC1 according to the sync mode configurated by the SYNCM 3 0 bits in ADC1_CTL0 register In sync mode when configure the conversion which is triggered by an external event the ADC1 m...

Page 279: ...in the ADC_CTL1 register A simultaneous trigger is provided to ADC1 At the end of conversion event on ADC0 or ADC1 an EOC interrupt is generated if enabled on one of the two ADC interfaces when the ADC0 ADC1 routine channels are all converted The behavior of routine parallel mode shows in the Figure 14 12 Routine parallel mode on 16 channels A 32 bit DMA is used which transfers ADC_RDATA 32 bit re...

Page 280: ...generated by ADC0 at the end of conversion event on ADC0 Also a 32 bit DMA can be used which transfers ADC_RDATA 32 bit register the ADC_RDATA 32 bit register containing the ADC1 converted data in the upper half word and the ADC0 converted data in the lower half word to SRAM Note The maximum sampling time allowed is 7 CK_ADC cycles to avoid the overlap between ADC0 and ADC1 sampling phases in the ...

Page 281: ...ted data in the upper half word and the ADC0 converted data in the lower half word to SRAM Note The maximum sampling time allowed is 14 CK_ADC cycles to avoid the overlap between ADC0 and ADC1 sampling phases in the event that they convert the same channel Figure 14 14 Routine follow up slow mode on 1 channel CH1 ADC0 ADC1 Routine trigger Sample Convert EOC ADC0 EOC ADC1 CH1 CH1 CH1 CH1 CH1 CH1 CH...

Page 282: ...ening Set by hardware when the converted voltage crosses the values programmed in the ADC_WDT1 register Cleared by software writing 0 to it 29 5 Reserved Must be kept at reset value 4 STRC Start flag of routine sequence 0 Conversion is not started 1 Conversion is started Set by hardware when routine sequence conversion starts Cleared by software writing 0 to it 31 5 Reserved Must be kept at reset ...

Page 283: ... WDE1IE Interrupt enable for WDE1 0 WDE1 interrupt disable 1 WDE1 interrupt enable 29 24 Reserved Must be kept at reset value 23 RWD0EN Routine channel analog watchdog 0 enable 0 Analog watchdog 0 disable 1 Analog watchdog enable 22 20 Reserved Must be kept at reset value 19 16 SYNCM 3 0 Sync mode selection These bits use to select the operating mode 0000 Free mode 0110 Routine parallel mode only ...

Page 284: ... EOCIE Interrupt enable for EOC 0 Interrupt disable 1 Interrupt enable 4 0 WD0CHSEL 4 0 Analog watchdog 0 channel select 00000 ADC channel0 00001 ADC channel1 00010 ADC channel2 00011 ADC channel 3 00100 ADC channel 4 00101 ADC channel 5 00110 ADC channel 6 00111 ADC channel 7 01000 ADC channel 8 01001 ADC channel 9 01010 ADC channel 10 01011 ADC channel 11 01100 ADC channel 12 01101 ADC channel 1...

Page 285: ...N Channel 16 temperature sensor enable of ADC0 0 Channel 16 of ADC0 disable 1 Channel 16 of ADC0 enable 22 SWRCST Software start conversion of routine sequence Set 1 on this bit starts a conversion of a routine sequence if ETSRC is 1 It is set by software and cleared by software or by hardware immediately after the conversion starts 21 Reserved Must be kept at reset value 20 ETERC External trigger...

Page 286: ...changed from low to high and take a stabilization time When this bit is high and 1 is written to it with other bits of this register unchanged the conversion will start 0 ADC disable and power down 1 ADC enable 14 7 4 Sample time register 0 ADC_SAMPT0 Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved...

Page 287: ... 5 Sample time register 1 ADC_SAMPT1 Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved SPT9 2 0 SPT8 2 0 SPT7 2 0 SPT6 2 0 SPT5 2 1 rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPT5 0 SPT4 2 0 SPT3 2 0 SPT2 2 0 SPT1 2 0 SPT0 2 0 rw rw rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must b...

Page 288: ...er 0 ADC_WDHT0 Address offset 0x24 Reset value 0x0000 0FFF This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved WDHT0 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 WDHT0 11 0 High threshold for analog watchdog 0 These bits define the high threshold for the analog wa...

Page 289: ...RSQ12 4 0 rw rw rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 20 RL 3 0 Routine sequence length The total number of conversion in routine sequence equals to RL 3 0 1 19 15 RSQ15 4 0 refer to RSQ0 4 0 description 14 10 RSQ14 4 0 refer to RSQ0 4 0 description 9 5 RSQ13 4 0 refer to RSQ0 4 0 description 4 0 RSQ12 4 0 refer to RSQ0 4 0 description 14 7 9 Routine sequence...

Page 290: ...rd 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RSQ5 4 0 RSQ4 4 0 RSQ3 4 1 rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSQ3 0 RSQ2 4 0 RSQ1 4 0 RSQ0 4 0 rw rw rw rw Bits Fields Descriptions 31 30 Reserved Must be kept at reset value 29 25 RSQ5 4 0 refer to RSQ0 4 0 description 24 20 RSQ4 4 0 refer to RSQ0 4 0 description 19 15 RSQ3 4 0 refer to RSQ0 4 0 description 14 10 RSQ2...

Page 291: ...ch is read only 14 7 12 Oversample control register ADC_OVSAMPCTL Address offset 0x80 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DRES 1 0 Reserved TOVS OVSS 3 0 OVSR 2 0 Reserved OVSEN rw rw rw rw rw Bits Fields Descriptions 31 14 Reserved Must be kept at reset value...

Page 292: ...es are reserved Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing 4 2 OVSR 2 0 Oversampling ratio This bit filed defines the number of oversampling ratio 000 2x 001 4x 010 8x 011 16x 100 32x 101 64x 110 128x 111 256x Note Software is allowed to write this bit only when ADCON 0 which ensures that no conversion is ongoing 1 Reserved Must be kept...

Page 293: ...s monitored by AWD1 When AWD1CH 17 0 000 0 the analog Watchdog 1 is disabled Note 1 The channels selected by AWD1CS must be also selected into the ADC_RSQn 2 Software is allowed to write these bits only when the ADC is disabled ADCON 0 14 7 14 Watchdog threshold register 1 ADC_WDT1 Address offset 0xA8 Reset value 0x00FF 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 2...

Page 294: ...Reserved Must be kept at reset value 7 0 WDLT1 7 0 Low threshold for analog watchdog 1 These bits define the low threshold for the analog watchdog 1 Note Software is allowed to write these bits only when the ADC is disabled ADCON 0 ...

Page 295: ...ty 15 2 Characteristics 8 bit or 12 bit resolution Right or left data alignment DMA support Conversion update synchronously Conversion trigged by external triggers Configurable internal buffer Extern voltage reference VREF Noise wave LFSR noise mode and Triangle noise mode Figure 15 1 DAC block diagram shows the block diagram of DAC and Table 15 1 DAC gives the pin description Figure 15 1 DAC bloc...

Page 296: ...hich is turned on by default can be turned off by setting the DBOFF bits in the DAC_CTL register Note In high temperature environments it is recommended to turn on the output buffer by setting the DBOFF bit to 0 15 3 3 DAC data configuration The 12 bit DAC holding data can be configured by writing any one of the OUT_R12DH OUT_L12DH and OUT_R8DH registers When the data is loaded by OUT_R8DH registe...

Page 297: ... by the DWM bits in the DAC_CTL register The amplitude of the noise can be configured by the DAC noise wave bit width DWBW bits in the DAC_CTL register LFSR noise wave mode there is a Linear Feedback Shift Register LFSR in the DAC control logic it controls the LFSR noise signal which is added to the OUT_DH value and then the result is stored into the OUT_DO register When the configured DAC noise w...

Page 298: ...15 3 8 DMA request When the external trigger is enabled the DMA request is enabled by setting the DDMAEN bits of the DAC_CTL register A DAC DMA request will be generated when an external hardware trigger not a software trigger occurs If a second external trigger arrives before the acknowledgement of the previous request the new request will not be serviced and an underrun error event occurs The DD...

Page 299: ...s off DBOFF 1 Otherwise DAC is connected to the external pin and to on chip peripherals CMP 13 DDUDRIE DAC_OUT DMA underrun interrupt enable 0 DAC_OUT DMA underrun interrupt disabled 1 DAC_OUT DMA underrun interrupt enabled 12 DDMAEN DAC_OUT DMA enable 0 DAC_OUT DMA mode disabled 1 DAC_OUT DMA mode enabled 11 8 DWBW 3 0 DAC_OUT noise wave bit width These bits specify bit width of the noise wave si...

Page 300: ...ction These bits are only used if bit DTEN 1 and select the external event used to trigger DAC 00 EXTRIG external trigger from TRIGSEL 01 Software trigger All other values Reserved 2 DTEN DAC_OUT trigger enable 0 DAC_OUT trigger disabled 1 DAC_OUT trigger enabled 1 DBOFF DAC_OUT output buffer turn off 0 DAC_OUT output buffer turns on to reduce the output impedance and improve the driving capabilit...

Page 301: ...rved OUT_DH 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 OUT_DH 11 0 DAC_OUT 12 bit right aligned data These bits specify the data that is to be converted by DAC_OUT 15 4 4 DAC_OUT 12 bit left aligned data holding register OUT_L12DH Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 ...

Page 302: ...OUT 8 bit right aligned data These bits specify the MSB 8 bits of the data that is to be converted by DAC_OUT 15 4 6 DAC_OUT data output register OUT_DO Address offset 0x14 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved OUT_DO 11 0 r Bits Fields Descriptions 31 12 Reserv...

Page 303: ...12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DDUDR Reserved rc_w1 Bits Fields Descriptions 31 14 Reserved Must be kept at reset value 13 DDUDR DAC_OUT DMA underrun flag set by hardware cleared by software write 1 0 No underrun occurred 1 Underrun occurred Speed of DAC trigger is high than the DMA transfer 12 0 Reserved Must be kept at reset value ...

Page 304: ...t environment and lower timing accuracy The Free watchdog timer generate a reset when the internal down counter reaches 0 or the counter is refreshed when the value of the counter is greater than the window register value The register write protection function in free watchdog can be enabled to prevent it from changing the configuration unexpectedly 16 1 2 Characteristics Free running 12 bit down ...

Page 305: ...s 0x0000 0FFF so if it is not updated the window option is disabled A reload operation is performed in order to reset the downcounter to the FWDGT_RLD value and the prescaler counter to generate the next reload as soon as the window value is changed The free watchdog can automatically start at power on when the hardware free watchdog bit in the device option bits is set To avoid reset the software...

Page 306: ...638 025 1 32 011 0 025 3276 025 1 64 100 0 025 6552 025 1 128 101 0 025 13104 025 1 256 110 or 111 0 025 26208 025 The FWDGT timeout can be more accurately by calibrating the IRC40K Note When after the execution of watchdog reload operation if the MCU needs enter the deepsleep standby mode immediately more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep standby...

Page 307: ...0x5555 Disable the FWDGT_PSC FWDGT_RLD and FWDGT_WND write protection 0xCCCC Start the free watchdog timer counter When the counter reduces to 0 the free watchdog generates a reset 0xAAAA Reload the counter Prescaler register FWDGT_PSC Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserve...

Page 308: ...7 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RLD 11 0 rw Bits Fields Descriptions 31 12 Reserved Must be kept at reset value 11 0 RLD 11 0 Free watchdog timer counter reload value Write 0xAAAA in the FWDGT_CTL register will reload the FWDGT conter with the RLD value These bits are write protected Write 0X5555 to the FWDGT_CTL register before writing these bits During a write operat...

Page 309: ... Free watchdog timer prescaler value update During a write operation to FWDGT_PSC register this bit is set and the value read from FWDGT_PSC register is invalid Window register FWDGT_WND Address offset 0x10 Reset value 0x0000 0FFF This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ...

Page 310: ... are used by the application it is mandatory to wait until WUD bit has been reset before changing the window value However after updating the window value it is not necessary to wait until WUD is reset before continuing code execution except in case of low power mode entry Before entering low power mode it is necessary to wait until WUD is reset ...

Page 311: ...is suitable for the situation that requires an accurate timing 16 2 2 Characteristics Programmable free running 7 bit down counter Generate reset in two conditions when WWDGT is enabled Reset when the counter reached 0x3F The counter is refreshed when the value of the counter is greater than the window register value Early wakeup interrupt EWI the watchdog is started and the interrupt is enabled t...

Page 312: ... enabled by setting the EWIE bit in the WWDGT_CFG register and the interrupt will be generated when the counter reaches 0x40 The software can do something such as communication or data logging in the interrupt service routine ISR in order to analyse the reason of software malfunctions or save the important data before resetting the device Moreover the software can reload the counter in ISR to mana...

Page 313: ...T 6 0 0x40 Max timeout value CNT 6 0 0x7F 1 1 00 81 92 μs 5 24 ms 1 2 01 163 84 μs 10 49 ms 1 4 10 327 68 μs 20 97 ms 1 8 11 655 36 μs 41 94 ms If the WWDGT_HOLD bit in DBG module is cleared the WWDGT continues to work even the Cortex M33 core halted Debug mode While the WWDGT_HOLD bit is set the WWDGT stops in Debug mode ...

Page 314: ... enabled 6 0 CNT 6 0 The value of the watchdog timer counter A reset occur when the value of this counter decreases from 0x40 to 0x3F When the value of this counter is greater than the window value writing this counter also causes a reset Configuration register WWDGT_CFG Address offset 0x04 Reset value 0x0000 007F This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 2...

Page 315: ...er than the Window value Status register WWDGT_STAT Address offset 0x08 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EWIF rc_w0 Bits Fields Descriptions 31 1 Reserved Must be kept at reset value 0 EWIF Early wakeup interrupt flag When the counter reach...

Page 316: ...source HXTAL clock divided by 128 LXTAL oscillator clock IRC40K oscillator clock Maskable interrupt source Alarm interrupt Second interrupt Overflow interrupt 17 3 Function overview The RTC circuits consist of two major units APB interface located in PCLK1 clock domain and RTC core located in RTC clock domain APB Interface is connected with the APB1 bus It includes a set of registers can be access...

Page 317: ...ading The APB interface and RTC core are located in two different power supply domains In the RTC core only counter and divider registers are readable registers And the values in the two registers and the RTC flags are internally updated at each rising edge of the RTC clock which is resynchronized by the APB1 clock When the APB interface is immediately enabled from a disable state the read operati...

Page 318: ...flag assertion Before the update of the RTC Counter the RTC second interrupt flag SCIF is asserted on the last RTCCLK cycle Before the counter equal to the RTC Alarm value which stored in the Alarm register increases by one the RTC Alarm interrupt flag ALRMIF is asserted on the last RTCCLK cycle Before the counter equals to 0x0 the RTC Overflow interrupt flag OVIF is asserted on the last RTCCLK cy...

Page 319: ...19 Figure 17 3 RTC second and overflow waveform example RTC_PSC 3 RTC_ Overflow FFFFFFFD FFFFFFFE FFFFFFFF 0 1 RTC_Second RTC_ CNT OVIF RTC_PSC OVIF flag can be cleared by software RTCCLK 2 3 1 0 3 1 1 3 3 2 1 0 2 0 2 0 2 1 ...

Page 320: ... kept at reset value 2 OVIE Overflow interrupt enable 0 Disable overflow interrupt 1 Enable overflow interrupt 1 ALRMIE Alarm interrupt enable 0 Disable alarm interrupt 1 Enable alarm interrupt 0 SCIE Second interrupt enable 0 Disable second interrupt 1 Enable second interrupt 17 4 2 RTC control register RTC_CTL Address offset 0x04 Reset value 0x0000 0020 This register can be accessed by half word...

Page 321: ...rm event not detected 1 Alarm event detected An interrupt named RTC global interrupt will occur if the ALRMIE bit is set in RTC_INTEN And another interrupt named the RTC Alarm interrupt will occur if the EXTI 17 is enabled in interrupt mode 0 SCIF Second interrupt flag 0 Second event not detected 1 Second event detected An interrupt will occur if the SCIE bit is set in RTC_INTEN Set by hardware wh...

Page 322: ... by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DIV 19 16 r Bits Fields Descriptions 31 4 Reserved Must be kept at reset value 3 0 DIV 19 16 RTC divider value high 17 4 6 RTC divider low register RTC_DIVL Address offset 0x14 Reset value 0x0000 8000 This register can be accessed by half word 16 bit or word 3...

Page 323: ...lf word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 31 16 rw 17 4 8 RTC counter low register RTC_CNTL Address offset 0x1C Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits ...

Page 324: ...M 31 16 w 17 4 10 RTC alarm low register RTC_ALRML Address offset 0x24 Reset value 0x0000 FFFF This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ALRM 15 0 w Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 ALRM 31 16 RTC alarm value high Bits Fields Descriptions 31 ...

Page 325: ...unt mode UP DOWN Center aligned UP DOWN Center aligned UP ONLY Repetition Channel Capture Compare 8 4 0 Complementary Dead time Break Single Pulse Quadrature Decoder Master slave management Inter Connection 1 1 TRGO TO DAC DMA 2 Debug Mode 1 Please refer to Trigger selection controller TRIGSEL for more details 2 Only update events will generate a DMA request TIMER5 6 do not have DMAS bit DMA reque...

Page 326: ...er width 16 bits Selectable clock source internal clock internal trigger external input external trigger Multiple counter modes up counting down counting and center aligned counting Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor function used for 3 phase motor control Programmable prescaler 16 bits The factor can be changed ongoing...

Page 327: ...t BRKIN0 BRKIN1 BRKIN2 BRKIN3 Polarity sele ction Filter TIMERx_CH1 TIMERx_CH2 TIMERx_CH3 TIMERx_MCH2 TIMERx_MCH1 TIMERx_MCH3 TIMERx_TG TIMERx_UP TIMERx_CMT Output Logic generation of outputs signals in compare PWM and mixed modes according to initialization complementary mode deadtime insertion break input output mask and polarity control APB BUS MCH0_IN MCH1_IN MCH2_IN MCH3_IN CH0_IN CH1_IN CH2_...

Page 328: ...nal input pin is selected as timer clock source The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin TIMERx_CHn TIMERx_MCHn n 0 3 This mode can be selected by setting SMC 2 0 to 0x7 and the TRGS 3 0 to 0x4 0x6 and 0x8 0xD And the counter prescaler can also be driven by rising edge on the internal trigger input pin ITI0 1...

Page 329: ...EN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler shadow 94 95 96 97 98 99 0 2 0 2 0 1 2 0 1 2 0 1 PSC value UPG 0 2 0 1 2 Counter up counting In this mode the counter counts up continuously from 0 to the counter reload value which is defined in the TIMERx_CAR register in a count up direction Once the counter reaches the counter reload value the counter will start counting up from 0 again an...

Page 330: ... mode PSC 0 2 and Figure 18 5 Timing chart of up counting mode change TIMERx_CAR on the go show some examples of the counter behavior for different clock prescaler factors when TIMERx_CAR 0x63 Figure 18 4 Timing chart of up counting mode PSC 0 2 CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF CNT_REG 96 Update event UPE Update interrupt flag UPIF H...

Page 331: ...unter reaches to 0 the counter the counter will start counting down from the counter reload value again and an underflow event will be generated In addition the update event will be generated after TIMERx_CREP 1 times of underflow The counting direction bit DIR in the TIMERx_CTL0 register should be set to 1 for the down counting mode When the update event is set by the UPG bit in the TIMERx_SWEVG ...

Page 332: ...are set PSC 0 PSC 2 TIMER_CK 91 PSC_CLK 2 1 0 99 98 Figure 18 7 Timing chart of down counting mode change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 5 4 3 2 1 0 99 98 97 96 95 94 93 92 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 5 4 3 2 1 0 99 1 0 120 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule...

Page 333: ...ill initialize the counter value to 0 and generate an update event irrespective of whether the counter is counting up or down in the center aligned counting mode The UPIF bit in the TIMERx_INTF register will be set to 1 either when an underflow event or an overflow event occurs While the CHxIF bit is associated with the value of CAM 1 0 in TIMERx_CTL0 The details refer to Figure 18 8 Timing chart ...

Page 334: ...etition is used to generator update event or updates the timer registers only after a given number N 1 of cycles of the counter where N is CREP in TIMERx_CREP register The repetition counter is decremented at each counter overflow does not exist in down counting mode and underflow does not exist in up counting mode Setting the UPG bit in the TIMERx_SWEVG register will reload the content of CREP in...

Page 335: ...the overflow Figure 18 9 Repetition counter timing chart of center aligned counting mode CEN 3 2 1 0 1 2 98 99 98 2 1 0 Underflow Overflow TIMERx_CREP 0x0 TIMER_CK 1 2 98 99 98 2 UPIF TIMERx_CREP 0x1 1 0 1 2 98 99 98 97 UPIF UPIF TIMERx_CREP 0x2 PSC_CLK Figure 18 10 Repetition counter timing chart of up counting mode CEN CNT_REG 96 97 98 99 0 1 98 99 0 1 98 99 Underflow Overflow TIMERx_CREP 0x0 TI...

Page 336: ...t channel x and multi mode channel x can perform input capture independently when the channels are used for comparison output the channel x and multi mode channel x can output independent mirrored and complementary outputs Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing frequency period duty cycle and so on The input sta...

Page 337: ...lock Prescaler Counter TIMER_CK Q Filter D Q D Q Edge Detector CI0FE0M ITS MCH0MS MCH0IF MCH0IE MCH0_CC_I TIMERx_CC_INT Capture INT From Other Channals MCH0CAPPSC Edge selector inverter Based on MCH0FP MCI0FE0M Rising Falling ITI0 ITI3 ITI1 ITI2 CI0FE0 Rising Falling IS0M CI0F_ED MCI1FEM0 TRGS The input signals of channelx CIx MCIx can be the TIMERx_CHx TIMERx_MCHxCV signal or the XOR signal of th...

Page 338: ...pt and DMA request Step5 Capture enable CHxEN and MCHxEN bits in TIMERx_CHCTL2 Result When the wanted input signal is captured TIMERx_CHxCV TIMERx_MCHxCV will be set by counter s value and CHxIF MCHxIF bit is asserted If the CHxIF MCHxIF bit is 1 the CHxOF MCHxOF bit will also be asserted The interrupt and DMA request will be asserted or not based on the configuration of CHxIE and CHxDEN bits MCHx...

Page 339: ...re register CHxCV Counter output comparator Compare output control CHxCOMCTL CNT CHxCV CNT CHxCV CNT CHxCV Output complementary protection register Dead Time Output enable and polarity selector CHxP CHxEN MCHxP MCHxEN OxCPRE CHx_O MCHx_O The relationship between the channel output signal CHx_O MCHx_O and the OxCPRE MOxCPRE signal more details refer to Channel output prepare signal is described as ...

Page 340: ...utput at the same time the specific outputs of CHx_O and MCHx_O are related to the relevant bits ROS IOS POEN and DTCFG bits in the TIMERx_CCHP register Please refer to Channel output complementary PWM for more details In channel output compare function the TIMERx can generate timed pulses with programmable position polarity duration and frequency When the counter matches the value in the TIMERx_C...

Page 341: ...er mode PWM can also be divided into EAPWM Edge aligned PWM and CAPWM Center aligned PWM The EAPWM s period is determined by TIMERx_CAR and the duty cycle is determined by TIMERx_CHxCV TIMERx_MCHxCV Figure 18 18 EAPWM timechart shows the EAPWM output and interrupts waveform The CAPWM s period is determined by 2 TIMERx_CAR and the duty cycle is determined by 2 TIMERx_CHxCV TIMERx_MCHxCV Figure 18 1...

Page 342: ... b11 up down CHxIF CHxOF Composite PWM mode In the Composite PWM mode CHxCPWMEN 1 b1 CHxMS 2 0 3 b000 and CHxCOMCTL 3 b110 or 3 b111 the PWM signal output in channel x x 0 3 is composited by CHxVAL and CHxCOMVAL_ADD bits If CHxCOMCTL 3 b110 PWM mode 0 and DIR 1 b0 up counting mode or CHxCOMCTL 3 b111 PWM mode 1 and DIR 1 b1 Down counting mode the channel x output is forced low when the counter mat...

Page 343: ...VAL CARL CHxCOMVAL_ADD PWM mode 0 up counting or PWM mode 1 down counting 100 PWM mode 0 down counting or PWM mode 1 up counting 0 CHxCOMVAL_ADD CARL CHxVAL PWM mode 0 up counting or PWM mode 1 down counting 0 PWM mode 0 down counting or PWM mode 1 up counting 100 CHxVAL CARL and CHxCOMVAL_ADD CARL The output of CHx_O is keeping When the counter reaches the value of CHxVAL the CHxIF bit is set and...

Page 344: ... and the value of CHxVAL and CHxCOMVAL_ADD between 0 and CARL Figure 18 21 Channel x output PWM with CHxVAL CHxCOMVAL_ADD 0 CHxVAL CHxCOMVAL_ADD CARL Constant 0 Constant 1 OxCPRE PWM MODE 1 Interrupt signal CHxIF OxCPRE PWM MODE 0 CHxCOMADDIF CARL Constant 0 Constant 1 OxCPRE PWM MODE 1 Interrupt signal CHxIF OxCPRE PWM MODE 0 CHxCOMADDIF CHxVAL CHxCOMVAL_ADD 0 Constant 0 CHxVAL CHxCOMVAL_ADD CARL...

Page 345: ...CPRE PWM MODE 0 CHxCOMADDIF 0 CHxVAL CARL CHxCOMVAL_ADD OxCPRE PWM MODE 1 Interrupt signal CHxIF OxCPRE PWM MODE 0 CHxCOMADDIF The composite PWM mode is intended to support the generation of PWM signals where the period is not modified while the signal is being generated but the duty cycle will be varied Figure 18 24 Channel x output PWM duty cycle changing with CHxCOMVAL_ADD shows the the PWM out...

Page 346: ...ach other pair to help eliminate noise generation The CHxVAL register value is the shift of the PWM pulse with respect to the beginning of counter period Figure 18 25 Four Channels outputs in Composite PWM mode 0 CARL O0CPRE CH0VAL CH1VAL CH0COMVAL_ADD CH2COMVAL_ADD CH2VAL CH1COMVAL_ADD CH3COMVAL_ADD CH3VAL O1CPRE O2CPRE O3CPRE PWM Mode 1 Output match pulse select Basing on that CHx_O x 0 3 output...

Page 347: ...en the match events occur and the pulse width is one CK_TIMER clock cycle CHxOMPSEL 2 b11 both the counter is counting up and counting down the OxCPRE signal is output a pulse when the match events occur and the pulse width is one CK_TIMER clock cycle Figure 18 26 CHx_O output with a pulse in edge aligned mode CHxOMPSEL 2 b00 0 CARL CHxVAL CHxCOMVAL _ADD OxCPRE CHxOMPSEL 2b 01 CHxOMPSEL 2b 10 CHxO...

Page 348: ... Refer to the definition of relative bit for more details Another special function of the OxCPRE signal is forced output which can be achieved by configuring the CHxCOMCTL field to 0x04 0x05 The output can be forced to an inactive active level irrespective of the comparison condition between the values of the counter and the TIMERx_CHxCV Configure the CHxCOMCEN bit to 1 in the TIMERx_CHCTL0 regist...

Page 349: ...1 1 0 0 1 0 0 CHx_O MCHx_O LOW CHx_O MCHx_O output disable 1 CHx_O LOW CHx_O output disable MCHx_O OxCPRE MCHxP MCHx_O output enable 1 0 CHx_O OxCPRE CHxP CHx_O output enable MCHx_O LOW MCHx_O output disable 1 CHx_O OxCPRE CHxP CHx_O output enable MCHx_O OxCPRE MCHxP MCHx_O output enable 1 0 0 CHx_O CHxP CHx_O output disable MCHx_O MCHxP MCHx_O output disable 1 CHx_O CHxP CHx_O output enable MCHx_...

Page 350: ... For example the dead time delay is greater than or equal to the duty cycle of the CHx_O signal then the CHx_O signal is always inactive As shown in Figure 18 28 Channel output complementary PWM with dead time insertion Figure 18 28 Channel output complementary PWM with dead time insertion 0 CHxVAL CARL OxCPRE CHx_O MCHx_O Deadtime Corner case Deadtime pulse width CHx_O MCHx_O Deadtime Pulse width...

Page 351: ...n chip comparator events configured in TRIGSEL module input by BRKIN0 pin Break events can also be generated by software using BRKG bit in the TIMERx_SWEVG register Figure 18 29 Break function diagram BRK0F Digital Filter BRK0EN 1 0 BRK0P BRKIN0 BRK3F Digital Filter BRK3EN 1 0 BRK3P BRKIN3 1 0 BRKP BRKEN BRKG Output Logic CKM clock monitor LVD_LOCK event LOCKUP_LOCK event SRAM ECC error event Refe...

Page 352: ...d dead time insertion and Break function The separated dead time insertion and break function for CHx_O and MCHx_O allows that each pair of channels has its own deadtime value and break function In this function CHx_O and MCHx_O are actually controlled by the IOS bit ROS bit and DTCFG 7 0 bits in TIMERx_FCCHPy y 0 3 register By configuring the FCCHPyEN y 0 3 bits in the TIMERx_FCCHPy y 0 3 registe...

Page 353: ...herefore users must configure the TIMERx_CAR register before the counter starts to count Table 18 5 Counting direction in different quadrature decoder mode Counting mode Level CI0FE0 CI1FE1 Rising Falling Rising Falling Quadrature decoder mode 0 SMC 2 0 3 b001 CI1FE1 1 Down Up CI1FE1 0 Up Down Quadrature decoder mode 1 SMC 2 0 3 b010 CI0FE0 1 Up Down CI0FE0 0 Down Up Quadrature decoder mode 2 SMC ...

Page 354: ...ed TIMER_out will generate PWM signals to control the speed of BLDC motor based on the ITIx Then the feedback circuit is finished you can change the configuration to fit your request Because the advanced general L0 TIMER has the input XOR function they can be used as the TIMER_in timer And the advanced timer has the functions of complementary output and dead time so it can be used as the TIMER_out...

Page 355: ...re Hall Sensor Rotor Position signals Driver Motor MCU BLDC Motor Figure 18 34 Hall sensor timing between two timers CH0VAL Counter CI0 OXR CH0_INPUT CH1_INPUT CH2_INPUT CH0_O MCH0_O CH1_O MCH1_O CH2_O MCH2_O Va Va Vb Vb Vc Vc Advanced General L0 TIMER_in under input capture mode Advanced TIMER_out under output compare mode PWM with Dead time ...

Page 356: ...r the polarity selection and inversion If ETIFP the filtered output of external trigger input ETI is selected as the trigger source configure the ETP for polarity selection and inversion For the ITIx no filter and prescaler can be used For the CIx filter can be used by configuring CHxCAPFLT no prescaler can be used For the ETIFP filter can be used by configuring ETFC and prescaler can be used by c...

Page 357: ...1 The ETI pin can select from TIMER_ETIx x 0 2 pins and each advanced TIMER only can use one of them Plese refer to TIMER input source select register SYSCFG_TIMERINSEL for more details Single pulse mode Single pulse mode is opposite to the repetitive mode which can be enabled by setting SPM in TIMERx_CTL0 When you set SPM the counter will be clear and stop when the next update event In order to g...

Page 358: ... as the compare match event occurs without taking the comparison result into account Single pulse mode is also applicable to composite PWM mode CHxCPWMEN 1 b1 and CHxMS 2 0 3 b000 Figure 18 38 Single pulse mode TIMERx_CHxCV 0x04 TIMERx_CAR 0x99 TIMER_CK PSC_CLK CEN CNT_REG 0 1 2 3 4 5 98 99 00 OxCPRE CI3 Under SPM counter stop Timers interconnection The timers can be internally connected for timer...

Page 359: ...odic signal on each counter overflow 2 Configure TIMER1 period TIMER1_CAR register 3 Select TIMER1 as TIMER0 input trigger source TRGS 3 b010 in the TIMERx_SMCFG register 4 Configure TIMER0 in external clock mode 0 SMC 3 b111 in TIMERx_SMCFG register 5 Start TIMER0 by writing 1 to the CEN bit TIMER0_CTL0 register 6 Start TIMER1 by writing 1 to the CEN bit TIMER1_CTL0 register Start TIMER0 with TIM...

Page 360: ...ER1 is triggered by its CI0 input rising edge To ensure that two timers start synchronously TIMER1 must be configured in master slave mode Steps are shown as follows 1 Configure TIMER1 in slave mode and select CI0F_ED as the input trigger TRGS 3 b100 in the TIMER1_SMCFG register 2 Configure TIMER1 in event mode SMC 3 b110 in the TIMER1_SMCFG register 3 Configure TIMER1 in master slave mode by writ...

Page 361: ... base address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB register is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer the timer sends only one DMA request While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer will send 3 more requests to DMA and DMA...

Page 362: ... between the CK_TIMER and the dead time and digital filter sample clock DTS 00 fDTS fCK_TIMER 01 fDTS fCK_TIMER 2 10 fDTS fCK_TIMER 4 11 Reserved 7 ARSE Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter align mode selection 00 No center aligned mode edge aligned mode The direction of the ...

Page 363: ... a DMA request The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event 1 This event generates update interrupts or DMA requests The counter generates an overflow or underflow event 1 UPDIS Update disable This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding sha...

Page 364: ... output Refer to ISO0N bit 10 ISO1 Idle state of channel 1 output Refer to ISO0 bit 9 ISO0N Idle state of multi mode channel 0 complementary output 0 When POEN bit is reset MCH0_O is set low 1 When POEN bit is reset MCH0_O is set high This bit can be modified only when PROT 1 0 bits in TIMERx_CCHP register is 00 8 ISO0 Idle state of channel 0 output 0 When POEN bit is reset CH0_O is set low 1 When...

Page 365: ... from O2CPRE 111 When a compare event occurs a TRGO trigger signal is output The compare source is from O3CPRE 3 DMAS DMA request source selection 0 When capture or compare event occurs the DMA request of channel x is sent 1 When update event occurs the DMA request of channel x is sent 2 CCUC Commutation control shadow register update control When the commutation control shadow registers for CHxEN...

Page 366: ...ive edge of the ETIFP signal 0 External clock mode 1 disabled 1 External clock mode 1 enabled When the slave mode is configured as restart mode pause mode or event mode the timer can still work in the external clock 1 mode by setting this bit But the TRGS bits must not be 3 b111 in this case The external clock input will be ETIFP if external clock mode 0 and external clock mode 1 are enabled at th...

Page 367: ...10 6 4 b1111 8 7 MSM Master slave mode This bit can be used to synchronize the selected timers to begin counting at the same time The TRGI is used as the start event and through TRGO timers are connected 0 Master slave mode disabled 1 Master slave mode enabled 6 4 TRGS 2 0 Trigger selection This bit field specifies which signal is selected as the trigger input to synchronize the timers 0000 Intern...

Page 368: ...nds on the level of the other CI1FE1 or CI0FE0 100 Restart mode The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input 101 Pause mode The trigger input enables the counter clock when it is high and disables the counter clock when it is low 110 Event mode A rising edge of the trigger input enables the counter 111 External clock mode 0 The coun...

Page 369: ...N 1 CH0MS 2 0 3 b000 and CH0COMCTL 3 b110 or 3 b111 27 MCH3DEN Multi mode channel 3 capture compare DMA request enable 0 Disabled 1 Enabled Note This bit just used for channel input and output independent mode when MCH3MSEL 1 0 2b 00 26 MCH2DEN Multi mode channel 2 capture compare DMA request enable 0 Disabled 1 Enabled Note This bit just used for channel input and output independent mode when MCH...

Page 370: ...H0IE Multi mode channel 0 capture compare interrupt enable 0 Disabled 1 Enabled Note This bit just used for channel input and output independent mode when MMCH0SEL 1 0 2b 00 19 15 Reserved Must be kept at reset value 14 TRGDEN Trigger DMA request enable 0 Disabled 1 Enabled 13 CMTDEN Commutation DMA request enable 0 Disabled 1 Enabled 12 CH3DEN Channel 3 capture compare DMA request enable 0 Disabl...

Page 371: ...nterrupt enable 0 Disabled 1 Enabled 0 UPIE Update interrupt enable 0 Disabled 1 Enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CH3COM ADDIF CH2COM ADDIF CH1COM ADDIF CH0COM ADDIF MCH3OF MCH2OF MCH1OF MCH0OF MCH3IF MCH2IF MCH1IF MCH0IF Reserved rc_w0 rc_w0 rc_w0 ...

Page 372: ...g Refer to MCH0OF description 25 MCH1OF Multi mode channel 1 over capture flag Refer to MCH0OF description 24 MCH0OF Multi mode channel 0 over capture flag When multi mode channel 0 is configured in input mode this flag is set by hardware when a capture event occurs while MCH0IF flag has already been set This flag is cleared by software 0 No over capture interrupt occurred 1 Over capture interrupt...

Page 373: ... flag When the break input is inactive the bit is set by hardware When the break input is inactive the bit can be cleared by software 0 No active level break has been detected 1 An active level has been detected 6 TRGIF Trigger interrupt flag This flag is set on trigger event and cleared by software When in pause mode both edges on trigger input generates a trigger event otherwise only an active e...

Page 374: ... 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CH3COM ADDG CH2COM ADDG CH1COM ADDG CH0COM ADDG Reserved MCH3G MCH2G MCH1G MCH0G Reserved w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G UPG w w w w w w w w Bits Fields Descriptions 31 CH3COMADDG Channel 3 additional compare event generation Refer to CH0COMADDG description 30 CH2COMADDG Chann...

Page 375: ...MCH0IF flag has been set 0 No generate a multi mode channel 0 capture or compare event 1 Generate a multi mode channel 0 capture or compare event 19 8 Reserved Must be kept at reset value 7 BRKG Break event generation This bit is set by software to generate an event and cleared by hardware automatically When this bit is set the POEN bit will be cleared and BRKIF flag will be set related interrupt ...

Page 376: ...apture or compare event 0 UPG Update event generation This bit can be set by software and automatically cleared by hardware When this bit is set the counter is cleared if the center aligned or up counting mode is selected while in down counting mode it takes the auto reload value The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Channel cont...

Page 377: ...l 1 compare output control Refer to CH0COMCTL description 11 CH1COMSEN Channel 1 output compare shadow enable Refer to CH0COMSEN description 10 Reserved Must be kept at reset value 9 8 CH1MS 1 0 Channel 1 mode selection This bit field specifies the direction of the channel and the input signal selection The CH1MS 2 0 bit field is writable only when the channel is not active When MCH1MSEL 1 0 2b 00...

Page 378: ... level 101 Force high O0CPRE is forced to high level 110 PWM mode 0 When counting up O0CPRE is active when the counter is smaller than TIMERx_CH0CV otherwise it is inactive When counting down O0CPRE is inactive when the counter is larger than TIMERx_CH0CV otherwise it is active 111 PWM mode 1 When counting up O0CPRE is inactive when the counter is smaller than TIMERx_CH0CV otherwise it is active W...

Page 379: ...in TIMERx_SMCFG register 100 Channel 0 is programmed as input IS0 is connected to MCI0FE0 101 111 Reserved Input capture mode Bits Fields Descriptions 31 CH1MS 2 Channel 1 I O mode selection Same as output compare mode 30 CH0MS 2 Channel 0 I O mode selection Same as output compare mode 29 16 Reserved Must be kept at reset value 15 12 CH1CAPFLT 3 0 Channel 1 input capture filter control Refer to CH...

Page 380: ...edge 01 The input capture occurs on every 2 channel input edges 10 The input capture occurs on every 4 channel input edges 11 The input capture occurs on every 8 channel input edges 1 0 CH0MS 1 0 Channel 0 I O mode selection Same as output compare mode Channel control register 1 TIMERx_CHCTL1 Address offset 0x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27...

Page 381: ...ue 15 CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14 12 CH3COMCTL 2 0 Channel 3 compare output control Refer to CH0COMCTL description 11 CH3COMSEN Channel 3 output compare shadow enable Refer to CH2COMSEN description 10 Reserved Must be kept at reset value 9 8 CH3MS 1 0 Channel 3 I O mode selection This bit field specifies the direction of the channel and the inp...

Page 382: ... is forced high when the counter is equals to the output compare register TIMERx_CH2CV 010 Clear the channel output on match O2CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH2CV 011 Toggle on match O2CPRE toggles when the counter is equals to the output compare register TIMERx_CH2CV 100 Force low O2CPRE is forced to low level 101 Force high O2CPRE is f...

Page 383: ... 0 2b 01 or 2b 11 the CH2EN and MCH2EN bits in TIMERx_CHCTL2 register are reset 00 Channel 2 is programmed as output 01 Channel 2 is programmed as input IS2 is connected to CI2FE2 10 Channel 2 is programmed as input IS2 is connected to CI3FE2 11 Channel 2 is programmed as input IS2 is connected to ITS This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SM...

Page 384: ...010 5 fDTS 16 4 b1011 6 4 b1100 8 4 b1101 5 fDTS 32 4 b1110 6 4 b1111 8 3 2 CH2CAPPSC 1 0 Channel 2 input capture prescaler This bit field specifies the factor of the prescaler on channel 2 input The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is cleared 00 Prescaler disabled capture is done on each channel input edge 01 The input capture occurs on every 2 channel input edges 10 Th...

Page 385: ...scription 9 CH2P Channel 2 capture compare polarity Refer to CH0P description 8 CH2EN Channel 2 capture compare enable Refer to CH0EN description 7 MCH1P Multi mode channel 1 output polarity Refer to MCH0P description 6 MCH1EN Multi mode channel 1 output enable Refer to MCH0EN description 5 CH1P Channel 1 capture compare polarity Refer to CH0P description 4 CH1EN Channel 1 capture compare enable R...

Page 386: ...nnel 0 input signal s rising edge is the active signal for capture or trigger operation in slave mode And channel 0 input signal will not be inverted 01 channel 0 input signal s falling edge is the active signal for capture or trigger operation in slave mode And channel 0 input signal will be inverted 10 Reserved 11 Noninverted both channel 0 input signal s edges This bit cannot be modified when P...

Page 387: ...31 16 Reserved Must be kept at reset value 15 0 PSC 15 0 Prescaler value of the counter clock The TIMER_CK clock is divided by PSC 1 to generate the counter clock The value of this bit field will be loaded to the corresponding shadow register at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 ...

Page 388: ...ifies the update event generation rate Each time the repetition counter counts down to zero an update event will be generated The update rate of the shadow registers is also affected by this bit field when these shadow registers are enabled Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 2...

Page 389: ...hen channel 1 is configured in input mode this bit field indicates the counter value at the last capture event And this bit field is read only When channel 1 is configured in output mode this bit field contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates by every update event Channel 2 capture compare value register TIMERx_CH2CV...

Page 390: ... 15 0 CH3VAL 15 0 Capture compare value of channel 3 When channel 3 is configured in input mode this bit field indicates the counter value at the last capture event And this bit field is read only When channel 3 is configured in output mode this bit field contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates by every update event...

Page 391: ...s the polarity of the BRKINx x 0 3 input signals 0 BRKINx x 0 3 input active low 1 BRKINx x 0 3 input active high This bit can be modified only when PROT 1 0 bit field in TIMERx_CCHP register is 00 12 BRKEN BRKINx x 0 3 input signals enable This bit can be set to enable the BRKINx x 0 3 and CKM clock failure event inputs 0 Break inputs disabled 1 Break inputs enabled This bit can be modified only ...

Page 392: ...egisters in PROT mode 0 the CHxP MCHxP bits in TIMERx_CHCTL2 register if related channel is configured in output mode the ROS IOS bits in TIMERx_CCHP register and the ROS IOS bits in TIMERx_FCCHPx x 0 3 register are writing protected 11 PROT mode 2 In addition to the registers in PROT mode 1 the CHxCOMCTL CHxCOMSEN CHxCOMADDSEN MCHxCOMCTL MCHxCOMSEN bits in TIMERx_CHCTL0 1 and TIMERx_MCHCTL0 1 reg...

Page 393: ...ription 14 12 MCH1COMCTL 2 0 Multi mode channel 1 compare output control Refer to MCH0COMCTL description 11 MCH1COMSEN Multi mode channel 1 output compare shadow enable Refer to MCH0COMSEN description 10 Reserved Must be kept at reset value 9 8 MCH1MS 1 0 Multi mode channel 1 I O mode selection This bit field specifies the direction of the channel and the input signal selection This bit field is w...

Page 394: ...t compare register TIMERx_MCH0CV 010 Clear the channel output on match MO0CPRE signal is forced low when the counter is equals tothe output compare register TIMERx_MCH0CV 011 Toggle on match MO0CPRE toggles when the counter is equals to the output compare register TIMERx_MCH0CV 100 Force low MO0CPRE is forced to low level 101 Force high MO0CPRE is forced to high level 110 PWM mode 0 When counting ...

Page 395: ...cted to ITS this mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMCFG register 100 Multi mode channel 0 is programmed as input MIS0 is connected to CI0FEM0 101 111 Reserved Input capture mode Bits Fields Descriptions 31 MCH1MS 2 Multi mode channel 1 I O mode selection Refer to MCH1MS 1 0 description 30 MCH0MS 2 Multi mode channel 0 I O mode selection Refe...

Page 396: ... input The prescaler is reset when MCH0EN bit in TIMERx_CHCTL2 register is cleared 00 Prescaler disable capture occurs on every active edge of the input signal 01 The capture input prescaler factor is 2 10 The capture input prescaler factor is 4 11 The capture input prescaler factor is 8 1 0 MCH0MS 1 0 Multi mode channel 0 I O mode selection Same as output compare mode Multi mode channel control r...

Page 397: ... bit in TIMERx_CHCTL2 register is reset 000 Multi mode channel 3 is programmed as output 01 Multi mode channel 3 is programmed as input MIS3 is connected to MCI3FEM3 010 Multi mode channel 3 is programmed as input MIS3 is connected to MCI2FEM3 011 Multi mode channel 3 is programmed as input MIS3 is connected to ITS this mode is working only if an internal trigger input is selected through TRGS bit...

Page 398: ...erwise it is active 111 PWM mode 1 When counting up MO2CPRE is inactive as long as the counter is smaller than TIMERx_MCH2CV otherwise it is active When counting down MO2CPRE is active as long as the counter is larger than TIMERx_MCH2CV otherwise it is inactive If configured in PWM mode the MO2CPRE level changes only when the output compare mode is adjusted from Timing mode to PWM mode or the comp...

Page 399: ...st be kept at reset value 15 12 MCH3CAPFLT 3 0 Multi mode channel 3 input capture filter control Refer to MCH2CAPFLT description 11 10 MCH3CAPPSC 1 0 Multi mode channel 3 input capture prescaler Refer to MCH2CAPPSC description 9 8 MCH3MS 1 0 Multi mode channel 3 I O mode selection Same as output compare mode 7 4 MCH2CAPFLT 3 0 Multi mode channel 2 input capture filter control The MCI2 input signal...

Page 400: ... O mode selection Same as output compare mode Multi mode channel control register 2 TIMERx_MCHCTL2 Address offset 0x50 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MCH3FP 1 0 MCH2FP 1 0 MCH1FP 1 0 MCH0FP 1 0 rw rw rw rw Bits Fields Descriptions 31 8 Re...

Page 401: ...de And multi mode channel 0 input signal will be inverted 10 Reserved 11 Noninverted both multi mode channel 0 input signal s edges This bit cannot be modified when PROT 1 0 bit field in TIMERx_CCHP register is 11 or 10 Multi mode channel 0 capture compare value register TIMERx_MCH0CV Address offset 0x54 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 2...

Page 402: ...o the counter When the corresponding shadow register is enabled the shadow register updates by every update event Multi mode channel 2 capture compare value register TIMERx_MCH2CV Address offset 0x5C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MCH2VAL 15 0 rw Bits Fields Descr...

Page 403: ...s bit field contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates by every update event Channel 0 additional compare value register TIMERx_CH0COMV_ADD Address offset 0x64 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 404: ...shadow register updates by every update event Note This register just used in composite PWM mode when CH1CPWMEN 1 Channel 2 additional compare value register TIMERx_CH2COMV_ADD Address offset 0x6C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH2COMVAL_ADD 15 0 rw Bits Fields De...

Page 405: ...hadow register updates by every update event Note This register just used in composite PWM mode when CH3CPWMEN 1 Control register 2 TIMERx_CTL2 Address offset 0x74 Reset value 0x0FF0 00FF This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CH3C PWMEN CH2C PWMEN CH1C PWMEN CH0C PWMEN MCH3MSEL 1 0 MCH2MSEL 1 0 MCH1MSEL 1 0 MCH0MSEL 1 0 Reserved rw rw rw rw...

Page 406: ...rrored mode just used for output the MCH1 output is the same as CH1 output 10 Reserved 11 Complementary mode only the CH1 is valid for input and the outputs of MCH1 and CH1 are complementary 21 20 MCH0MSEL 1 0 Multi mode channel 0 mode select 00 Independent mode MCH0 is independent of CH0 01 Mirrored mode just used for output the MCH0 output is the same as CH0 output 10 Reserved 11 Complementary m...

Page 407: ...1CPRE signal is output normal with the configuration of CH1COMCTL 2 0 bits 01 Only when the counter is counting up the O1CPRE signal is output a pulse when the match events occurs and the pulse width is one CK_TIMER clock cycle 10 Only when the counter is counting down the O1CPRE signal is output a pulse when the match events occurs and the pulse width is one CK_TIMER clock cycle 11 Both when the ...

Page 408: ...deadtime insertion in the outputs of MCH2_O and CH2_O 0 Disabled 1 Enabled 1 DTIENCH1 Dead time inserted enable for channel 1 Enables the deadtime insertion in the outputs of MCH1_O and CH1_O 0 Disabled 1 Enabled 0 DTIENCH0 Dead time inserted enable for channel 0 Enables the deadtime insertion in the outputs of MCH0_O and CH0_O 0 Disabled 1 Enabled Break configuration register TIMERx_BRKCFG Addres...

Page 409: ...ive high This bit can be modified only when PROT 1 0 bit field in TIMERx_CCHP register is 00 28 BRK2EN BRKIN2 input signal enable This bit can be set to enable the BRKIN2 input 0 Break inputs disabled 1 Break inputs enabled This bit can be modified only when PROT 1 0 bit field in TIMERx_CCHP register is 00 27 BRK1P BRKIN1 input signal polarity This bit specifies the polarity of the BRKIN1 input si...

Page 410: ...00 Filter disabled BRKIN3 act asynchronously N 1 0001 fSAMP fCK_TIMER N 2 0010 fSAMP fCK_TIMER N 4 0011 fSAMP fCK_TIMER N 8 0100 fSAMP fDTS 2 N 6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 This b...

Page 411: ...KIN1 act asynchronously N 1 0001 fSAMP fCK_TIMER N 2 0010 fSAMP fCK_TIMER N 4 0011 fSAMP fCK_TIMER N 8 0100 fSAMP fDTS 2 N 6 0101 fSAMP fDTS 2 N 8 0110 fSAMP fDTS 4 N 6 0111 fSAMP fDTS 4 N 8 1000 fSAMP fDTS 8 N 6 1001 fSAMP fDTS 8 N 8 1010 fSAMP fDTS 16 N 5 1011 fSAMP fDTS 16 N 6 1100 fSAMP fDTS 16 N 8 1101 fSAMP fDTS 32 N 5 1110 fSAMP fDTS 32 N 6 1111 fSAMP fDTS 32 N 8 This bit can be modified on...

Page 412: ... 25 24 23 22 21 20 19 18 17 16 FCCHP0 EN Reserved rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved ROS IOS Reserved DTCFG 7 0 rw rw rw Bits Fields Descriptions 31 FCCHP0EN Free complementary channel protection register 0 enable 0 the ROS IOS and DTCFG 7 0 bits in TIMERx_CCHP register is active 1 the ROS IOS and DTCFG 7 0 bits in TIMERx_FCCHP0 register is active This bit can be modified only when ...

Page 413: ...dead time which is inserted before the output transitions The relationship between DTCFG value and the duration of dead time is as follow DTCFG 7 5 3 b0xx DTvalue DTCFG 7 0 x tDT tDT tDTS DTCFG 7 5 3 b10x DTvalue 64 DTCFG 5 0 xtDT tDT tDTS 2 DTCFG 7 5 3 b110 DTvalue 32 DTCFG 4 0 xtDT tDT tDTS 8 DTCFG 7 5 3 b111 DTvalue 32 DTCFG 4 0 xtDT tDT tDTS 16 This bit can be modified only when PROT 1 0 bit f...

Page 414: ... POEN bit is reset the channel output signals CH1_O MCH1_O are disabled 1 When POEN bit is reset he channel output signals CH1_O MCH1_O are enabled with relationship to CH1EN MCH1EN bits in TIMERx_CHCTL2 register This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 10 or 11 9 8 Reserved Must be kept at reset value 7 0 DTCFG 7 0 Dead time configure This bit field controls ...

Page 415: ..._O MCH2_O are enabled with relationship to CH2EN MCH2EN bits in TIMERx_CHCTL2 register This bit cannot be modified when PROT 1 0 bit filed in TIMERx_CCHP register is 10 or 11 10 IOS Idle mode off state configure When POEN bit is reset this bit specifies the output state for the channels which has been configured in output mode 0 When POEN bit is reset the channel output signals CH2_O MCH2_O are di...

Page 416: ...an be modified only when PROT 1 0 bit filed in TIMERx_CCHP register is 00 30 12 Reserved Must be kept at reset value 11 ROS Run mode off state configure When POEN bit is set this bit specifies the output state for the channels which has a complementary output and has been configured in output mode 0 When POEN bit is set the channel output signals CH3_O MCH3_O are disabled 1 When POEN bit is set th...

Page 417: ...MERx_DMACFG Address offset 0xE0 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DMATC 5 0 Reserved DMATA 5 0 rw rw Bits Fields Descriptions 31 14 Reserved Must be kept at reset value 13 8 DMATC 5 0 DMA transfer count This filed defines the number n of the register that DM...

Page 418: ...tart address transfer count 4 will be accessed The transfer count is calculated by hardware and ranges from 0 to DMATC Configuration register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL OUTSEL rw rw Bits Fields Descriptions 31 2 R...

Page 419: ...GD32A50x User Manual 419 This bit field is set and reset by software 1 If POEN bit and IOS bit are 0 the output is disabled 0 No effect ...

Page 420: ...k source internal clock internal trigger external input external trigger Multiple counter modes up counting down counting and center aligned counting Quadrature decoder used for motion tracking and determination of both rotation direction and position Hall sensor function used for 3 phase motor control Programmable prescaler 16 bits The factor can be changed ongoing Each channel is user configurab...

Page 421: ...tor Counter Quadrate Decoder 18 2 4 Function overview Clock source configuration The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC TIMERx_SMCFG bit 2 0 SMC 2 0 3 b000 Internal clock CK_TIMER is selected as timer clock source which is from module RCU The default clock source is the CK_TIMER for driving the counter pres...

Page 422: ...ternal clock mode 1 External input ETI is selected as timer clock source The TIMER_CK which drives counter s prescaler to count can be triggered by the event of rising or falling edge on the external pin ETI This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1 The other way to select the ETI signal as the clock source is setting the SMC 2 0 to 0x7 and the TRGS 2 0 to...

Page 423: ...h counter overflow The counting direction bit DIR in the TIMERx_CTL1 register should be set to 0 for the up counting mode Whenever if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register the counter value will be initialized to 0 and an update event will be generated If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an upd...

Page 424: ...CK 8 PSC_CLK 97 98 99 0 1 Figure 18 46 Timing chart of up counting change TIMERx_CAR on the go TIMER_CK CEN PSC_CLK CNT_REG 94 95 96 97 98 99 0 1 2 3 4 5 6 7 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule CNT_REG 113 114 115 116 117 118 119 120 0 1 2 98 99 0 Update event UPE Update interrupt flag UPIF Auto reload register 120 99 change CAR Vaule 120 99 Aut...

Page 425: ...he counter reload value and an update event will be generated If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the shadow registers counter autoreload register prescaler register are updated Figure 18 47 Timing chart of down counting mode PSC 0 2 and Figure 18 48 Timing chart of down counting mode change TIMERx_CAR on the go show some exa...

Page 426: ...e counter reload value subtract 1 in the up counting mode and generates an underflow event when the counter counts to 1 in the down counting mode The counting direction bit DIR in the TIMERx_CTL0 register is read only and indicates the counting direction when in the center aligned mode Setting the UPG bit in the TIMERx_SWEVG register will initialize the counter value to 0 and generate an update ev...

Page 427: ...he general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs Each channel is built around a channel capture compare register including an input stage channel controller and an output stage Channel input capture function Channel input capture function allows the channel to perform measurements such as pulse timing frequency period duty cycle and...

Page 428: ...s several input events generate one effective capture event On the capture event TIMERx_CHxCV will store the value of counter So the process can be divided into several steps as below Step1 Filter configuration CHxCAPFLT in TIMERx_CHCTL0 Based on the input signal and quality of requested signal configure compatible CHxCAPFLT Step2 Edge selection CHxP CHxNP in TIMERx_CHCTL2 Rising edge or falling e...

Page 429: ...ails refer to Channel output prepare signal is described as blew The active level of O0CPRE is high the output level of CH0_O depends on OxCPRE signal CHxP bit and CH0P bit please refer to the TIMERx_CHCTL2 register for more details For example configure CHxP 0 the active level of CHx_O is high the same as OxCPRE CHxEN 1 the output of CHx_O is enabled If the output of OxCPRE is active high level t...

Page 430: ...ch clear OxCPRE OxCPRE Output PWM function In the PWM output mode by setting the CHxCOMCTL bit to 3 b110 PWM mode 0 or to 3 b 111 PWM mode 1 the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers Based on the counter mode PWM can also be divided into EAPWM Edge aligned PWM and CAPWM Center aligned PWM The EAPWM s period is determined by TIMERx_CAR an...

Page 431: ...l CHxIF CHxOF CAM 2 b01 down only CAM 2 b10 up only CHxIF CHxOF CAM 2 b11 up down CHxIF CHxOF Channel output prepare signal As is shown in Figure 18 51 Channel output compare principle x 0 1 2 3 when TIMERx is configured in compare match output mode a middle signal which is OxCPRE signal Channel x output prepare signal will be generated before the channel outputs signal The OxCPRE signal type is d...

Page 432: ... decoder The quadrature decoder function uses two quadrature inputs CI0FE0 and CI1FE1 derived from the TIMERx_CH0 and TIMERx_CH1 pins respectively to interact with each other to generate the counter value Setting SMC 0x01 0x02 or 0x03 to select that the counting direction of timer is determined only by the CI0FE0 only by the CI1FE1 or by the CI0FE0 and the CI1FE1 The DIR bit is modified during the...

Page 433: ...des including restart mode pause mode and event mode which is selected by the SMC 2 0 bits in the TIMERx_SMCFG register The input trigger of these modes can be selected by the TRGS 2 0 bits in the TIMERx_SMCFG register Table 18 8 Examples of slave mode Mode Selection Source Selection Polarity Selection Filter and Prescaler LIST SMC 2 0 3 b100 restart mode 3 b101 pause mode 3 b110 event mode TRGS 2...

Page 434: ...put comes TRGS 2 0 3 b000 ITI0 is selected For ITI0 no polarity selector can be used For the ITI0 no filter and prescaler can be used Figure 18 57 Restart mode TIMER_CK CEN CNT_REG 5E 5F 60 61 62 63 00 01 02 03 04 00 01 02 UPIF ITI0 TRGIF Internal sync delay Exam2 Pause mode The counter will be paused when the trigger input is low and it will start when the trigger input is high TRGS 2 0 3 b101 CI...

Page 435: ...it is not necessary to configure the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter Setting the CEN bit to 1 or a trigger signal edge can generate a pulse and then keep the CEN bit at a high state until the update event occurs or the CEN bit is written to 0 by software If the CEN bit is cleared to 0 by software the counter will be stopped and its value will be held In ...

Page 436: ..._DMATB is configured to PADDR peripheral base address then DMA will access the TIMERx_DMATB In fact TIMERx_DMATB register is only a buffer timer will map the TIMERx_DMATB to an internal register appointed by the field of DMATA in TIMERx_DMACFG If the field of DMATC in TIMERx_DMACFG is 0 1 transfer the timer sends only one DMA request While if TIMERx_DMATC is not 0 such as 3 4 transfers then timer ...

Page 437: ...E Auto reload shadow enable 0 The shadow register for TIMERx_CAR register is disabled 1 The shadow register for TIMERx_CAR register is enabled 6 5 CAM 1 0 Counter align mode selection 00 No center aligned mode edge aligned mode The direction of the counter is specified by the DIR bit 01 Center aligned and counting down assert mode The counter counts in center aligned mode and channel is configured...

Page 438: ...ests The counter generates an overflow or underflow event 1 UPDIS Update disabled This bit is used to enable or disable the update event generation 0 Update event enable When an update event occurs the corresponding shadow registers are loaded with their preloaded values These events generate update event The UPG bit is set The counter generates an overflow or underflow event The restart mode gene...

Page 439: ...timer generate a reset the UPG bit in the TIMERx_SWEVG register is set 001 Enable When a conter start event occurs a TRGO trigger signal is output The counter start source CEN control bit is set The trigger input in pause mode is high 010 When an update event occurs a TRGO trigger signal is output The update source depends on UPDIS bit and UPS bit 011 When a capture or compare pulse event occurs i...

Page 440: ...the ETIFP signal 0 External clock mode 1 disabled 1 External clock mode 1 enabled When the slave mode is configured as restart mode pause mode or event mode the timer can still work in the external clock 1 mode by setting this bit But the TRGS bits must not be 3 b111 in this case The external clock input will be ETIFP if external clock mode 0 and external clock mode 1 are enabled at the same time ...

Page 441: ...101 5 fDTS_CK 32 4 b1110 6 4 b1111 8 7 MSM Master slave mode This bit can be used to synchronize the selected timers to begin counting at the same time The TRGI is used as the start event and through TRGO timers are connected together 0 Master slave mode disabled 1 Master slave mode enabled 6 4 TRGS 2 0 Trigger selection This bit field specifies which signal is selected as the trigger input to syn...

Page 442: ... The trigger input enables the counter clock when it is high and disables the counter clock when it is low 110 Event mode A rising edge of the trigger input enables the counter 111 External clock mode0 The counter counts on the rising edges of the selected trigger DMA and interrupt enable register TIMERx_DMAINTEN Address offset 0x0C Reset value 0x0000 0000 This register has to be accessed by word ...

Page 443: ... Disabled 1 Enabled 5 Reserved Must be kept at reset value 4 CH3IE Channel 3 capture compare interrupt enable 0 Disabled 1 Enabled 3 CH2IE Channel 2 capture compare interrupt enable 0 Disabled 1 Enabled 2 CH1IE Channel 1 capture compare interrupt enable 0 Disabled 1 Enabled 1 CH0IE Channel 0 capture compare interrupt enable 0 Disabled 1 Enabled 0 UPIE Update interrupt enable 0 Disabled 1 Enabled I...

Page 444: ... This flag is cleared by software 0 No over capture interrupt occurred 1 Over capture interrupt occurred 8 7 Reserved Must be kept at reset value 6 TRGIF Trigger interrupt flag This flag is set on trigger event and cleared by software When in pause mode both edges on trigger input generates a trigger event otherwise only an active edge on trigger input can generates a trigger event 0 No trigger ev...

Page 445: ... CH1G CH0G UPG w w w w w w Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 TRGG Trigger event generation This bit is set by software and cleared by hardware automatically When this bit is set the TRGIF flag in TIMERx_STAT register will be set related interrupt or DMA transfer can occur if enabled 0 No generate a trigger event 1 Generate a trigger event 5 Reserved Must be kept ...

Page 446: ...set 0x18 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH1COM CEN CH1COMCTL 2 0 CH1COM SEN Reserved CH1MS 1 0 CH0COM CEN CH0COMCTL 2 0 CH0COM SEN Reserved CH0MS 1 0 CH1CAPFLT 3 0 CH1CAPPSC 1 0 CH0CAPFLT 3 0 CH0CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descript...

Page 447: ...output on match O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV 011 Toggle on match O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV 100 Force low O0CPRE is forced to low level 101 Force high O0CPRE is forced to high level 110 PWM mode 0 When counting up O0CPRE is active when the counter is smaller than TIMERx_...

Page 448: ...value 15 12 CH1CAPFLT 3 0 Channel 1 input capture filter control Refer to CH0CAPFLT description 11 10 CH1CAPPSC 1 0 Channel 1 input capture prescaler Refer to CH0CAPPSC description 9 8 CH1MS 1 0 Channel 1 mode selection Same as output compare mode 7 4 CH0CAPFLT 3 0 Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit field configure the filteri...

Page 449: ...x1C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3COM CEN CH3COMCTL 2 0 CH3COM SEN Reserved CH3MS 1 0 CH2COM CEN CH2COMCTL 2 0 CH2COM SEN Reserved CH2MS 1 0 CH3CAPFLT 3 0 CH3CAPPSC 1 0 CH2CAPFLT 3 0 CH2CAPPSC 1 0 rw rw rw rw rw rw Output compare mode Bits Fields Descriptions ...

Page 450: ...nel output on match O2CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH2CV 010 Clear the channel output on match O2CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH2CV 011 Toggle on match O2CPRE toggles when the counter is equals to the output compare register TIMERx_CH2CV 100 Force low O2CPRE is forced to low...

Page 451: ...CFG register Input capture mode Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 12 CH3CAPFLT 3 0 Channel 3 input capture filter control Refer to CH0CAPFLT description 11 10 CH3CAPPSC 1 0 Channel 3 input capture prescaler Refer to CH0CAPPSC description 9 8 CH3MS 1 0 Channel 3 mode selection Same as output compare mode 7 4 CH2CAPFLT 3 0 Channel 2 input capture filter control T...

Page 452: ...0 Channel 2 mode selection Same as output compare mode Channel control register 2 TIMERx_CHCTL2 Address offset 0x20 Reset value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CH3NP Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved CH0P CH...

Page 453: ...in input mode in conjunction with CH0P this bit is used to define the polatity of CH0 This bit cannot be modified when PROT 1 0 bit field in TIMERx_CCHP register is 11 or 10 2 Reserved Must be kept at reset value 1 CH0P Channel 0 capture compare function polarity When channel 0 is configured in output mode this bit specifies the output signal polarity 0 Channel 0 active high 1 Channel 0 active low...

Page 454: ...30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 15 0 This bit field indicates the current counter value Writing to this bit field can change the value of the counter Prescaler register TIMERx_PSC Address offset 0x28 Reset value 0x0000 0000 This register has to be acc...

Page 455: ...e This bit field specifies the auto reload value of the counter Note When the timer is configured in input capture mode this register must be configured a non zero value such as 0xFFFF which is larger than user expected value Channel 0 capture compare value register TIMERx_CH0CV Address offset 0x34 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 2...

Page 456: ...en channel 1 is configured in input mode this bit field indicates the counter value at the last capture event And this bit field is read only When channel 1 is configured in output mode this bit field contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates by every update event Channel 2 capture compare value register TIMERx_CH2CV ...

Page 457: ...kept at reset value 15 0 CH3VAL 15 0 Capture compare value of channel 3 When channel3 is configured in input mode this bit field indicates the counter value at the last capture event And this bit field is read only When channel 3 is configured in output mode this bit field contains value to be compared to the counter When the corresponding shadow register is enabled the shadow register updates by ...

Page 458: ...ster TIMERx_DMATB Address offset 0xE4 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMATB 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 DMATB 15 0 DMA transfer buffer When a read or write operation is assigned to this register the register loca...

Page 459: ...n register TIMERx_CFG Address offset 0xFC Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved CHVSEL Reserved rw Bits Fields Descriptions 31 2 Reserved Must be kept at reset value 1 CHVSEL Write CHxVAL register selection This bit field set and reset by software 1 If write the...

Page 460: ...igure 18 61 Basic timer block diagram provides details on the internal configuration of the basic timer Figure 18 61 Basic timer block diagram PSC Trigger processor Trigger Selector Counter Counter Register Interrupt Register set and update Interrupt collector APB BUS CK_TIMER CAR TIMERx_TRGO Interrupt Update UPIE TIMER_CK PSC_CLK DMA controller DMA REQ ACK TIMERx_UP 18 3 4 Function overview Clock...

Page 461: ...nter clock PSC_CK is obtained by the TIMER_CK through the prescaler and the prescale factor can be configured from 1 to 65536 through the prescaler register TIMERx_PSC The new written prescaler value will not take effect until the next update event Figure 18 63 Timing chart of PSC value change from 0 to 2 TIMER_CK CEN PSC_CLK CNT_REG Reload Pulse Prescaler CNT Prescaler shadow 94 95 96 97 98 99 0 ...

Page 462: ...in the TIMERx_SWEVG register the counter value will be initialized to 0 and generates an update event If the UPDIS bit in TIMERx_CTL0 register is set the update event is disabled When an update event occurs all the shadow registers auto reload register prescaler register are updated The following figures show some examples of the counter behavior for different clock prescaler factor when TIMERx_CA...

Page 463: ...gle pulse mode Single pulse mode is opposite to the repetitive mode which can be enabled by setting SPM in TIMERx_CTL0 When you set SPM the counter will be clear and stop when the next update event Once the timer is set to operate in the single pulse mode it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter then the CEN bit keeps at a high state un...

Page 464: ...ved Must be kept at reset value 3 SPM Single pulse mode 0 Single pulse mode is disabled Counter continues after an update event 1 Single pulse mode is enabled The counter counts until the next update event occurs 2 UPS Update source This bit is used to select the update event sources by software 0 These events generate an update interrupt or a DMA request The UPG bit is set The counter generates a...

Page 465: ...1 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved MMC 2 0 Reserved rw Bits Fields Descriptions 31 7 Reserved Must be kept at reset value 6 4 MMC 2 0 Master mode control These bits control the selection of TRGO signal which is sent by master timer to slave timer for synchronization function 000 When a counter reset event occurs a TRGO trigger signal is output The counter rese...

Page 466: ...0 Disabled 1 Enabled 7 1 Reserved Must be kept at reset value 0 UPIE Update interrupt enable 0 Disabled 1 Enabled Interrupt flag register TIMERx_INTF Address offset 0x10 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved UPIF rc_w0 Bits Fields Descriptions 31 1 Reserved Must...

Page 467: ...leared The prescaler counter is cleared at the same time 0 No generate an update event 1 Generate an update event Counter register TIMERx_CNT Address offset 0x24 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at res...

Page 468: ...ter at every update event Counter auto reload register TIMERx_CAR Address offset 0x2C Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CARL 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CARL 15 0 Counter auto reload value This bit field specifies ...

Page 469: ... mode and hardware flow control protocol CTS RTS The data frame can be transferred from LSB or MSB bit The polarity of the TX RX pins can be configured independently and flexibly All USARTs support DMA function for high speed data communication 19 2 Characteristics NRZ standard format Asynchronous full duplex communication Half duplex single wire communications Receive FIFO function Dual clock dom...

Page 470: ... RBNE receive FIFO full RFF Transmit buffer empty TBE transfer complete TC Flags for error detection overrun error ORERR noise error NERR frame error FERR and parity error PERR Flag for hardware flow control CTS changes CTSF Flag for LIN mode LIN break detected LBDF Flag for multiprocessor communication IDLE frame detected IDLEF Flag for ModBus communication Address character match AMF and receive...

Page 471: ...RTDIV 8 2 OVSMOD USART Baud Rate Register UCLK Transmitter clock Receiver clock Write Buffer Read Buffer Read FiFO 19 3 1 USART frame format The USART frame starts with a start bit and ends up with a number of stop bits The length of the data frame is configured by the WL bit in the USART_CTL0 register The last data bit can be used as parity check bit by setting the PCEN bit of in USART_CTL0 regis...

Page 472: ...f a 12 bit integer and a 4 bit fractional part The number formed by these two values is used by the baud rate generator to determine the bit period Having a fractional baud rate divider allows the USART to generate all the standard baud rates The baud rate divider USARTDIV has the following relationship with the peripheral clock In case of oversampling by 16 the equation is USARTDIV UCLK 16 Baud R...

Page 473: ... cleared and set soon because the data will be transferred to the transmit shift register immediately If a frame is transmitted and the TBE bit is asserted the TC bit of the USART_STAT register will be set An interrupt will be generated if the corresponding interrupt enable bit TCIE is set in the USART_CTL0 register The USART transmit procedure is shown in Figure 19 3 USART transmit procedure The ...

Page 474: ...d if the corresponding interrupt enable bit RBNEIE is set in the USART_CTL0 register The status of the reception are stored in the USART_STAT register The software can get the received data by reading the USART_RDATA register directly or through DMA The RBNE bit is cleared by a read operation on the USART_RDATA register whatever it is performed by software directly or through DMA The REN bit shoul...

Page 475: ...e 0 5 stop bit part is not sampled and sampling in the middle of 1 stop bit 2 stop bits When 2 stop bits if a frame error is detected during the first stop bit the frame error flag is set the second stop bit is not checked frame error If no frame error is detected during the first stop bit then continue to check the second stop bit for frame error When a frame is received if the RBNE bit is not cl...

Page 476: ...riority etc Clear the TC bit in USART_STAT Enable the DMA channel for USART Wait the TC bit to be set After all of the data frames are transmitted the TC bit in USART_STAT is set An interrupt occurs if the TCIE bit in USART_CTL0 is set When DMA is used for USART reception DMA transfers data from the receive data buffer of the USART to the internal SRAM The configuration steps are shown in Figure 1...

Page 477: ...annel for USART When the number of the data received by USART reaches the DMA transfer number an end of transfer interrupt can be generated in the DMA module 19 3 6 Hardware flow control The hardware flow control function is realized by the nCTS and nRTS pins The RTS flow control is enabled by writing 1 to the RTSEN bit in USART_CTL2 and the CTS flow control is enabled by writing 1 to the CTSEN bi...

Page 478: ... the USART_CTL2 control register allows the user to activate the external transceiver control through the DE Driver Enable signal The assertion time which is programmed using the DEA 4 0 bits field in the USART_CTL0 control register is the time between the activation of the DE signal and the beginning of the START bit The de assertion time which is programmed using the DED 4 0 bits field in the US...

Page 479: ... In these situations the RBNE bit is not set If the frame defers from the ADDR_DATA bits in the USART_CTL1 register the hardware sets the RWU bit and enters mute mode automatically In this situation the RBNE bit is not set If the PCEN bit in USART_CTL0 is set the MSB bit will be checked as the parity bit and the bit preceding the MSB bit is detected as the address or data bit When the USART will b...

Page 480: ...us mode The USART can be used for full duplex synchronous serial communications only in master mode by setting the CKEN bit in USART_CTL1 The LMEN bit in USART_CTL1 and SCEN HDEN IREN bits in USART_CTL2 should be cleared in synchronous mode The CK pin is the clock output of the synchronous USART transmitter and can be only activated when the TEN bit is enabled No clock pulse will be sent through t...

Page 481: ...6 bit7 bit0 bit1 bit2 bit3 CK pin CPL 0 CPH 0 19 3 10 IrDA SIR ENDEC mode The IrDA mode is enabled by setting the IREN bit in USART_CTL2 The LMEN STB 1 0 CKEN bits in USART_CTL1 and HDEN SCEN bits in USART_CTL2 should be cleared in IrDA mode In IrDA mode the USART transmission data frame is modulated in the SIR transmit encoder and transmitted to the infrared LED through the TX pin The SIR receive...

Page 482: ...C clock While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times of PSC clock Because the IrDA is a half duplex protocol the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block Figure 19 14 IrDA data modulation Nomal tx frame Stop Start 1 0 0 0 0 0 0 1 1 1 1 Stop Start 1 0 1 1 1 1 0 0 0 0 0 TX pin Nomal rx...

Page 483: ...t is set The clock can be divided for other use The frame consists of 1 start bit 9 data bits 1 parity bit included and 1 5 stop bits The smartcard mode is a half duplex communication protocol When connected to a smartcard the TX pin must be configured as open drain mode and drives a bidirectional line that is also driven by the smartcard Figure 19 15 ISO7816 3 frame format 0 1 2 3 4 5 6 7 0 1 2 3...

Page 484: ...o deactivate the NACK transmission When requesting a read from the smartcard the RT 23 0 bits in USART_RT register should be programmed with the BWT block wait time 11 value and RBNEIE must be set A timeout interrupt will be generated if no answer is received from the card before the expiration of this period If the first character is received before the expiration of the period it is signaled by ...

Page 485: ...f block detection In the ModBus RTU mode the end of one block is recognized by an idle line for more than 2 characters time This function is implemented through the programmable timeout function To detect the idle line the RTEN bit in the USART_CTL1 register and the RTIE in the USART_CTL0 register must be set The USART_RT register must be set to the value corresponding to a timeout of 2 characters...

Page 486: ... When using the standard RBNE interrupt the RBNEIE bit must be set before entering Deep sleep mode When using the WUIE interrupt the source of WUIE interrupt may be selected through the WUM bit fields DMA must be disabled before entering Deep sleep mode Before entering Deep sleep mode software must check that the USART is not performing a transfer by checking the BSY flag in the USART_STAT registe...

Page 487: ...LIN mode LBDF LBDIE Reception Errors Noise flag overrun error framing error NERR or ORERR or FERR ERRIE Character match AMF AMIE Receiver timeout error RTF RTIE End of Block EBF EBIE Wakeup from Deep sleep mode WUF WUIE All of the interrupt events are ORed together before being sent to the interrupt controller so the USART can only generate a single interrupt request to the controller at any given...

Page 488: ...8 Figure 19 17 USART interrupt mapping diagram IDLEF IDLEIE RBNE RBNEIE ORERR RBNEIE PERR PERRIE WUF WUIE LBDF LBDIE AMF AMIE RTF RTIE EBF EBIE FERR NERR ORERR ERRIE OR TC TCIE TBE TBEIE CTSF CTSIE USART_INT RFFINT RFFIE DMA ...

Page 489: ...method 00 Idle line 01 Address match 1x Data match This bit field cannot be written when the USART is enabled UEN 1 27 EBIE End of Block interrupt enable 0 End of Block interrupt is disabled 1 End of Block interrupt is enabled 26 RTIE Receiver timeout interrupt enable 0 Receiver timeout interrupt is disabled 1 Receiver timeout interrupt is enabled 25 21 DEA 4 0 Driver Enable assertion time These b...

Page 490: ... WM0 Wakeup method in mute mode this bit with bit 28 determines the wakeup method This bit field cannot be written when the USART is enabled UEN 1 10 PCEN Parity control enable 0 Parity control disabled 1 Parity control enabled This bit field cannot be written when the USART is enabled UEN 1 9 PM Parity mode 0 Even parity 1 Odd parity This bit field cannot be written when the USART is enabled UEN ...

Page 491: ...ep sleep mode 1 USART able to wake up the MCU from Deep sleep mode Providing that the clock source for the USART must be IRC16M or LXTAL 0 UEN USART enable 0 USART prescaler and outputs disabled 1 USART prescaler and outputs enabled 19 4 2 Control register 1 USART_CTL1 Address offset 0x04 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19...

Page 492: ...EN 1 18 DINV Data bit level inversion 0 Data bit signal values are not inverted 1 Data bit signal values are inverted This bit field cannot be written when the USART is enabled UEN 1 17 TINV TX pin level inversion 0 TX pin signal values are not inverted 1 TX pin signal values are inverted This bit field cannot be written when the USART is enabled UEN 1 16 RINV RX pin level inversion 0 RX pin signa...

Page 493: ... MSB is not output to the CK pin in synchronous mode 1 The clock pulse of the last data bit MSB is output to the CK pin in synchronous mode This bit field cannot be written when the USART is enabled UEN 1 7 Reserved Must be kept at reset value 6 LBDIE LIN break detection interrupt enable 0 LIN break detection interrupt is disabled 1 An interrupt will occur whenever the LBDF bit is set in USART_STA...

Page 494: ...he WUF Wakeup from Deep sleep mode flag in the USART_STAT register 00 WUF active on address or data match which is defined by ADDR_DATA 7 0 bits and ADDM bit 01 Reserved 10 WUF active on Start bit 11 WUF active on RBNE This bit field cannot be written when the USART is enabled UEN 1 19 17 SCRTNUM 2 0 Smartcard auto retry number In smartcard mode these bits specify the number of retries in transmis...

Page 495: ...BNE before clearing the error flag This bit field cannot be written when the USART is enabled UEN 1 12 OVRD Overrun disable 0 Overrun functionality is enabled The ORERR error flag will be set when received data is not read before receiving new data and the new data will be lost 1 Overrun functionality is disabled The ORERR error flag will not be set when received data is not read before receiving ...

Page 496: ...led UEN 1 3 HDEN Half duplex enable 0 Half duplex mode is disabled 1 Half duplex mode is enabled This bit field cannot be written when the USART is enabled UEN 1 2 IRLP IrDA low power 0 Normal mode 1 Low power mode This bit field cannot be written when the USART is enabled UEN 1 1 IREN IrDA mode enable 0 IrDA disabled 1 IrDA enabled This bit field cannot be written when the USART is enabled UEN 1 ...

Page 497: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GUAT 7 0 PSC 7 0 rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 8 GUAT 7 0 Guard time value in smartcard mode This bit field cannot be written when the USART is enabled UEN 1 7 0 PSC 7 0 Prescaler value for dividing the system clock In IrDA Low power mode the division factor...

Page 498: ...lue which must be programmed only once per received block can be programmed after the start of the block reception using the data from the LEN character in the Prologue Field The block length counter is reset when TBE 0 in smartcard mode In other modes when REN 0 receiver disabled and or when the EBC bit is written to 1 the Block length counter is reset 23 0 RT 23 0 Receiver timeout threshold Thes...

Page 499: ...rs the RBNE flag to discard the received data without reading it 2 MMCMD Mute mode command Writing 1 to this bit makes the USART into mute mode and sets the RWU flag 1 SBKCMD Send break command Writing 1 to this bit sets the SBKF flag and makes the USART send a BREAK frame as soon as the transmit machine is idle 0 Reserved Must be kept at reset value 19 4 8 Status register USART_STAT Address offse...

Page 500: ...the USART_INTC register This bit can also be cleared when UESM is cleared 19 RWU Receiver wakeup from mute mode This bit is used to indicate if the USART is in mute mode 0 Receiver in active mode 1 Receiver in mute mode It is cleared set by hardware when a wakeup mute sequence address or IDLEIE is recognized which is selected by the WAKE bit in the USART_CTL0 register This bit can only be set by w...

Page 501: ...s to the CWT or BWT timings in smartcard mode 10 CTS CTS level This bit equals to the inverted level of the nCTS input pin 0 nCTS input pin is in high level 1 nCTS input pin is in low level 9 CTSF CTS change flag 0 No change occurred on the nCTS status line 1 A change occurred on the nCTS status line An interrupt will occur if the CTSIE bit is set in USART_CTL2 Set by hardware when the nCTS input ...

Page 502: ...DLEIE bit is set in USART_CTL0 Set by hardware when an Idle Line is detected It will not be set again until the RBNE bit has been set itself Cleared by writing 1 to IDLEC bit in USART_INTC register 3 ORERR Overrun error 0 No Overrun error is detected 1 Overrun error is detected An interrupt will occur if the RBNEIE bit is set in USART_CTL0 In multibuffer communication an interrupt will occur if th...

Page 503: ...TC Address offset 0x20 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved WUC Reserved AMC Reserved w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved EBC RTC Reserved CTSC LBDC Reserved TCC Reserved IDLEC OREC NEC FEC PEC w w w w w w w w w w Bits Fields Descriptions 31 21 Reserved Must be kept at reset value 20 WUC Wake...

Page 504: ...riting 1 to this bit clears the NERR bit in the USART_STAT register 1 FEC Frame error flag clear Writing 1 to this bit clears the FERR bit in the USART_STAT register 0 PEC Parity error clear Writing 1 to this bit clears the PERR bit in the USART_STAT register 19 4 10 Receive data register USART_RDATA Address offset 0x24 Reset value Undefined This register has to be accessed by word 32 bit 31 30 29...

Page 505: ... will be replaced by the parity when transmitting with the parity is enabled PCEN bit set to 1 in the USART_CTL0 register This register must be written only when TBE bit in USART_STAT register is set 19 4 12 USART coherence control register USART_CHC Address offset 0xC0 Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ...

Page 506: ... 7 6 5 4 3 2 1 0 RFFINT RFCNT 2 0 RFF RFE RFFIE RFEN Reserved ELNACK r_w0 r r r rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 RFFINT Receive FIFO full interrupt flag 14 12 RFCNT 2 0 Receive FIFO counter number 11 RFF Receive FIFO full flag 0 Receive FIFO not full 1 Receive FIFO full 10 RFE Receive FIFO empty flag 0 Receive FIFO not empty 1 Receive FIFO empty 9 RFF...

Page 507: ...32A50x User Manual 507 The NACK pulse occurs 1 16 bit time earlier when the parity error is detected 0 Early NACKdisable when smartcard mode is selected 1 Early NACKenable when smartcard mode is selected ...

Page 508: ...duce CPU overload 20 2 Characteristics Parallel bus to I2C bus protocol converter and interface Both master and slave functions with the same interface Bi directional data transfer between master and slave Supports 7 bit and 10 bit addressing and general call addressing Multiple 7 bit slave addresses 2 address 1 with configurable mask Programmable setup time and hold time Multi master capability S...

Page 509: ... the device which receives data from the bus Master the device which initiates a transfer generates clock signals and terminates a transfer Slave the device addressed by a master Multi master more than one master can attempt to control the bus at the same time without corrupting the message Arbitration procedure to ensure that if more than one master tries to control the bus simultaneously only on...

Page 510: ...e transmitter Slave receiver Master transmitter Master receiver Data validation The data on the SDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW see Figure 20 2 Data validation One clock pulse is generated for each data bit transferred Figure 20 2 Data validation SDA SCL START and STOP si...

Page 511: ...ral Call is enabled by software the I2C slave always responses to a General Call Address 0x00 The I2C block support both 7 bit and 10 bit address modes Data and addresses are transferred as 8 bit bytes MSB first The first byte s following the START signalcontain the address one in 7 bit mode two in 10 bit mode The address is always transmitted in master mode A 9th clock pulse follows the 8 clock c...

Page 512: ...low with 10 bit address Master Receive when HEAD10R 0 In 10 bit addressing mode if the master reception follows a master transmission between the same master and slave the address read sequence can be RESTART header of 10 bit address in read direction as is shown in Figure 20 8 I2C communication flow with 10 bit address Master Receive when HEAD10R 1 Figure 20 7 I2C communication flow with 10 bit a...

Page 513: ...of the SCL or the SDA will be changed if the level is stable for more than DNF 3 0 tI2CCLK The length of spikes to be suppressed is configured by DNF 3 0 20 3 4 I2C timings configuration The PSC 3 0 SCLDELY 3 0 and SDADELY 3 0 bits in the I2C_TIMING register must be configured in order to guarantee a correct data hold and setup time used in I2C communication If the data is already available in I2C...

Page 514: ... should be less than the maximum of tVD DAT When SS 0 after tSDADELY delay the slave had to stretch the clock before the data writing to I2C_TDATA register SCL is low during the data setup time The setup time is tSCLDELY SCLDELY 1 tPSC tSCLDELY effects tSU DAT SCLDELY must match condition as follows SCLDELY tr max tSU DAT min PSC 1 tI2CCLK 1 In master mode the SCL clock high and low levels must be...

Page 515: ...re START STOP NACKEN in I2C_CTL1 register I2CBSY TBE TI RBNE ADDSEND NACK TCR TC STPDET BERR LOSTARB and OUERR in I2C_STAT register Additionally when the SMBus is supported PECTRANS in I2C_CTL1 register PECERR TIMEOUT and SMBALT in I2C_STAT are also impacted In order to perform the software reset I2CEN must be kept low during at least 3 APB clock cycles This is ensured by writing software sequence...

Page 516: ...until the previous received data in I2C_RDATA is read The stretch is inserted before the acknowledge pulse Figure 20 12 Data reception I2C_RDATA SCL Shift register xx data1 xx data2 xx RBNE data0 data1 data2 ACK pulse ACK pulse read data0 read data1 SCL Stretch Reload and automatic end mode In order to manage byte transfer and to shut down the communication in modes as is shown in Table 20 3 Commu...

Page 517: ...must be cleared 20 3 7 I2C slave mode Initialization When works in slave mode at least one slave address should be enabled Slave address 1 can be programmed in I2C_SADDR0 register and slave address 2 can be programmed in I2C_SADDR1 register ADDRESSEN in I2C_SADDR0 register and ADDRESS2EN in I2C_SADDR1 register should be set when the corresponding address is used 7 bit address or 10 bit address can...

Page 518: ...STPDET bit is set and the first data transmission starts OUERR bit in the I2C_STAT register will also be set In slave receiving mode before the 9th SCL pulse ACK pulse occurred by the next data byte the data must be read out from the I2C_RDATA register Or else the OUERR bit in the I2C_STAT register will be set if the ERRIE bit is set and an interrupt will be generated Slave byte control mode In sl...

Page 519: ... 7 1 ADDMSK2 2 0 and ADDRESS2EN in I2C_SADDR1 ADDM 6 0 in I2C_CTL2 Configure SBCTL in I2C_CTL0 Programming model in slave transmitting mode When the I2C_TDATA register is empty the TI bit in I2C_STAT register will be set If the TIE bit in I2C_CTL0 register is set an interrupt will be generated The NACK bit in I2C_STAT register will be set when a NACK is received And an interrupt is generated if th...

Page 520: ...r The STPDET must be 0 when the data transmission begins Or else the OUERR bit in I2C_STAT register will be set and an underrun error occurs When interrupt or DMA is used in slave transmitter if a TI event is needed in order to generate a TI event both the TI bit and the TBE bit must be set Figure 20 14 Programming model for slave transmitting when SS 0 IDLE Master generates START condition Master...

Page 521: ...et TI Write DATA 3 to I2C_TDATA Write DATA 4 to I2C_TDATA Write DATA N to I2C_TDATA Set TI I2C Line State Hardware Action Software Flow Slave sends DATA 1 Master sends Acknowledge Write DATA N 1 to I2C_TDATA DATA N 1 will not be sent Clear STPDET Write DATA 1 to I2C_TDATA Set TI Slave sends DATA N Master don t send ACK Set TI TBE and NACK Clear NACK Set TBE Programming model in slave receiving mod...

Page 522: ...H 7 0 are used for the low level counting and high level couting respectively After a tSYNC1 delay when the SCL low level is detected the SCLL 7 0 starts counting if the SCLL 7 0 in I2C_TIMING register is reached by SCLL 7 0 counter the I2C will release the SCL clock After a tSYNC2 delay when the SCL high level is detected the SCLH 7 0 starts counting if the SCLH 7 0 in I2C_TIMING register is reac...

Page 523: ...ion of 10 bit header the master will resend it until ACK is received The ADDSENDC bit must be set to stop sending the slave address If the START bit is set meanwhile the ADDSEND is set by addressing as a slave the master changes to slave mode The ADDSENDC bit must be set to clear the START bit Figure 20 17 I2C initialization in master mode I2CEN 0 Configure DNF 3 0 in I2C_CTL0 START Configure PSC ...

Page 524: ...et an interrupt will be generated Note When the RELOAD bit is 1 the AUTOEND has no effect Figure 20 18 Programming model for master transmitting N 255 IDLE Master generates START condition Master sends Address Slave sends Acknowledge Wait for ACK from slave Master sends DATA 1 Slave sends Acknowledge Data transmission Master sends DATA N 2 Slave sends Acknowledge Master sends DATA N Slave sends Ac...

Page 525: ...ite DATA 2 to I2C_TDATA Write DATA 3 to I2C_TDATA Write DATA N to I2C_TDATA Master sends DATA N 1 Slave sends Acknowledge Set TI Master sends DATA N Slave sends Acknowledge Set TC Programming model in master receiving mode In master receiving mode the RBNE bit in I2C_STAT register will be set when a byte is received If the RBNEIE bit is set in I2C_CTL0 register an interrupt will be generated If th...

Page 526: ...TA 1 Master sends Acknowledge Data transmission Slave sends DATA N Master don t send ACK Master generates STOP condition Software initialization Set RBNE Set RBNE Read DATA x Set RBNE Read DATA 1 Slave sends DATA N 1 Master sends Acknowledge Set RBNE Read DATA N set STOP I2C Line State Hardware Action Software Flow Set START Read DATA N 1 AUTOEND 0 BYTENUM 7 0 N ...

Page 527: ... Acknowledge Set RBNE Read DATA N Read DATA N 1 Set STOP 20 3 9 SMBus support The System Management Bus abbreviated to SMBus or SMB is a single ended simple two wire bus for the purpose of lightweight communication Most commonly it is found in computer motherboards for communication with power source for ON OFF instructions It is derived from I2C for communication with low bandwidth devices on a m...

Page 528: ...MBus host address Time out feature SMBus has a time out feature which resets devices if a communication takes too long This explains the minimum clock frequency of 10 kHz to prevent locking up the bus I2C can be a DC bus meaning that a slave device stretches the master clock when performing some routine while the master is accessing it This will notify to the master that the slave is busy but does...

Page 529: ...e When PECTRANS is set and the RELOAD bit is cleared PEC is transmitted after the BYTENUM 7 0 1 data byte The PECTRANS has no effect if RELOAD is set Table 20 4 SMBus with PEC configuration Mode SBCTL bit RELOAD bit AUTOEND bit PECTRANS bit Master Tx Rx BYTENUM PEC STOP x 0 1 1 Master Tx Rx BYTENUM PEC RESTART x 0 0 1 Slave Tx Rx with PEC 1 0 x 1 SMBus alert The SMBus has an extra optional shared ...

Page 530: ...uld be enabled when needed The SMBus Device Default address 0b1100 001 is enabled by setting the SMBDAEN bit in the I2C_CTL0 register The SMBus Host address 0b0001 000 is enabled by setting the SMBHAEN bit in the I2C_CTL0 register The Alert Response Address 0b0001 100 is enabled by setting the SMBALTEN bit in the I2C_CTL0 register 20 3 10 SMBus mode SMBus Master Transmitter and Slave Receiver The ...

Page 531: ...al on the bus PECTRANS bit must be set and slave addresses must be programmed After receiving BYTENUM 1 data the next received byte will be compared with the data in the I2C_PEC register automatically A NACK is respond to the PEC byte before STOP signal If the SMBus master receiver is required to generate a RESTART signal after receiving PEC byte the software mode AUTOEND 0 must be selected Before...

Page 532: ...gister In slave mode the DMA must be initialized before the address match event or in the ADDSEND interrupt routine before clearing the ADDSEND flag 20 3 12 I2C error and interrupts The I2C error flags are listed in Table 20 5 I2C error flags Table 20 5 I2C error flags I2C Error Name Description BERR Bus error LOSTARB Arbitration lost OUERR Overrun Underrun flag PECERR CRC value doesn t match TIME...

Page 533: ... 533 20 3 13 I2C debug mode When the microcontroller enters the debug mode Cortex M33 core halted the SMBus timeout either continues to work normally or stops depending on the I2Cx_HOLD configuration bits in the DBG module ...

Page 534: ...set value 23 PECEN PEC Calculation Switch 0 PEC Calculation off 1 PEC Calculation on 22 SMBALTEN SMBus Alert enable 0 SMBA pin is not pulled down device mode or SMBus Alert pin SMBA is disabled host mode 1 SMBA pin is pulled down device mode or SMBus Alert pin SMBA is enabled host mode 21 SMBDAEN SMBus device default address enable 0 Device default address is disabled the default address 0b1100001...

Page 535: ...t reset value 12 ANOFF Analog noise filter disable 0 Analog noise filter is enabled 1 Analog noise filter is disabled Note This bit can only be programmed when the I2C is disabled I2CEN 0 11 8 DNF 3 0 Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input The digital filter will filter spikes with a length of up to DNF 3 0 tI2CCLK 0000 Digital filter is...

Page 536: ...interrupt enable 0 Transmit TI interrupt is disabled 1 Transmit TI interrupt is enabled 0 I2CEN I2C peripheral enable 0 I2C is disabled 1 I2C is enabled 20 4 2 Control register 1 I2C_CTL1 Address offset 0x04 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved PECTRA NS AUTOEN D RELOAD BYTENUM 7 0 rw rw rw rw 15 14 13 12 11 1...

Page 537: ...en the START bit is set 15 NACKEN Generate NACK in slave mode 0 an ACK is sent after receiving a new byte 1 a NACK is sent after receiving a new byte Note The bit can be set by software and cleared by hardware when the NACK is sent or when a STOP signal is detected or ADDSEND is set or when I2CEN 0 When PEC is enabled whether to send an ACK or a NACK is not depend on the NACKEN bit When SS 1 and t...

Page 538: ...ADD10EN 1 these bits should be written with bits 9 8 of the slave address to be sent SADDRESS 7 1 Slave address bit 7 1 If ADD10EN 0 these bits should be written with the 7 bit slave address to be sent If ADD10EN 1 these bits should be written with bits 7 1 of the slave address to be sent SADDRESS0 Slave address bit 0 If ADD10EN 0 this bit has no effect If ADD10EN 1 this bit should be written with...

Page 539: ...it should not be written 20 4 4 Slave address register 1 I2C_SADDR1 Address offset 0x0C Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDRES S2EN Reserved ADDMSK2 2 0 ADDRESS2 7 1 Reserved rw rw rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 ADDRESS2EN Se...

Page 540: ... 6 5 4 3 2 1 0 SCLH 7 0 SCLL 7 0 rw rw Bits Fields Descriptions 31 28 PSC 3 0 Timing prescaler In order to generate the clock period tPSC used for data setup and data hold counters these bits are used to configure the prescaler for I2CCLK The tPSC is also used for SCL high and low level counters tPSC PSC 1 tI2CCLK 27 24 Reserved Must be kept at reset value 23 20 SCLDELY 3 0 Data setup time A delay...

Page 541: ...than tLOW EXT a timeout error will be occurred tLOW EXT BUSTOB 1 2048 tI2CCLK 0 Extended clock timeout detection is disabled 1 Extended clock timeout detection is enabled 30 28 Reserved Must be kept at reset value 27 16 BUSTOB Bus timeout B Configure the cumulative clock extension timeout In master mode the master cumulative clock low extend time tLOW MEXT is detected In slave mode the slave cumul...

Page 542: ...r r r r r r rw rw Bits Fields Descriptions 31 24 Reserved Must be kept at reset value 23 17 READDR 6 0 Received match address in slave mode When the ADDSEND bit is set these bits store the matched address In the case of a 10 bit address READDR 6 0 stores the header of the 10 bit address followed by the 2 MSBs of the address 16 TR Whether the I2C is a transmitter or a receiver in slave mode This bi...

Page 543: ... SS 1 when an overrun underrun error occurs this bit will be set by hardware It is cleared by software by setting the OUERRC bit and cleared by hardware when I2CEN 0 0 No overrun or underrun occurs 1 Overrun or underrun occurs 9 LOSTARB Arbitration Lost It is cleared by software by setting the LOSTARBC bit and cleared by hardware when I2CEN 0 0 No arbitration lost 1 Arbitration lost occurs and the...

Page 544: ...d cleared by hardware when I2CEN 0 0 Received address not matched 1 Received address matched 2 RBNE I2C_RDATA is not empty during receiving This bit is set by hardware when the received data is shift into the I2C_RDATA register It is cleared when I2C_RDATA is read 0 I2C_RDATA is empty 1 I2C_RDATA is not empty software can read 1 TI Transmit interrupt This bit is set by hardware when the I2C_TDATA ...

Page 545: ...iting 1 to this bit 11 PECERRC PEC error flag clear Software can clear the PECERR bit of I2C_STAT by writing 1 to this bit 10 OUERRC Overrun Underrun flag clear Software can clear the OUERR bit of I2C_STAT by writing 1 to this bit 9 LOSTARBC Arbitration Lost flag clear Software can clear the LOSTARB bit of I2C_STAT by writing 1 to this bit 8 BERRC Bus error flag clear Software can clear the BERR b...

Page 546: ... when PEC is enabled PECV is cleared by hardware when I2CEN 0 20 4 10 Receive data register I2C_RDATA Address offset 0x24 Reset value 0x0000 0000 This register can be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved RDATA 7 0 r Bits Fields Descriptions 31 8 Reserved Must be kept at reset value 7 0 RDATA 7 0 Receive data...

Page 547: ...bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADDM 6 0 Reserved rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 9 ADDM 6 0 Defines which bits of ADDRESS 7 1 are compared with an incoming address byte and which bits are ignored Any bit set to 1 in ADDM 6 0 enables comparisons with the corresponding bit in ADDRESS 7 1 Bit...

Page 548: ...2 1 SPI characteristics Master or slave operation with full duplex or simplex mode Separate transmit and receive buffer 16 bits wide Data frame size can be 8 or 16 bits Bit order can be LSB or MSB Software and hardware NSS management Hardware CRC calculation transmission and checking Transmission and reception using DMA SPI TI mode supported SPI NSS pulse mode supported Quad SPI configuration avai...

Page 549: ...rection Description SCK I O Master SPI clock output Slave SPI clock input MISO I O Master Data reception line Slave Data transmission line Master with bidirectional mode Not used Slave with bidirectional mode Data transmission and reception line MOSI I O Master Data transmission line Slave Data reception line Master with bidirectional mode Data transmission and reception line Slave with bidirectio...

Page 550: ...I signal description Pin name Direction Description SCK O SPI clock output MOSI I O Transmission Reception data 0 MISO I O Transmission Reception data 1 IO2 I O Transmission Reception data 2 IO3 I O Transmission Reception data 3 NSS O NSS output 21 3 3 SPI clock timing and data format CKPL and CKPH bits in SPI_CTL0 register decide the timing of SPI clock and data signal The CKPL bit decides the SC...

Page 551: ... Slave mode When slave mode is configured MSTMOD 0 SPI gets NSS level from NSS pin in hardware NSS mode SWNSSEN 0 or from SWNSS bit in software NSS mode SWNSSEN 1 and SPI transmits receives data only when NSS level is low In software NSS mode NSS pin is not used Table 21 3 NSS function in slave mode Mode Register configuration Description Slave hardware NSS mode MSTMOD 0 SWNSSEN 0 SPI slave gets N...

Page 552: ...hardware NSS input mode MSTMOD 1 SWNSSEN 0 NSSDRV 0 Applicable to multi master mode At this time NSS is configured as hardware input mode Once the NSS pin is pulled low SPI will automatically enter slave mode and a master configuration error will occur and the CONFERR bit will be set to 1 Master software NSS mode MSTMOD 1 SWNSSEN 1 SWNSS 0 NSSDRV Don t care Applicable to multi master mode Once SWN...

Page 553: ...DEN 1 BDOEN 0 MOSI Reception MISO Not used SFD Slave full duplex MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI Reception MISO Transmission STU Slave transmission with unidirectional connection MSTMOD 0 RO 0 BDEN 0 BDOEN Don t care MOSI Not used MISO Transmission SRU Slave reception with unidirectional connection MSTMOD 0 RO 1 BDEN 0 BDOEN Don t care MOSI Reception MISO Not used STB Slave transmission...

Page 554: ...simplex connection Master Receive Slave Transmit Master MRU MISO MOSI SCK NSS Slave STU MISO MOSI SCK NSS Figure 21 6 A typical simplex connection Master Transmit only Slave Receive Master MTU MISO MOSI SCK NSS Slave SRU MISO MOSI SCK NSS Figure 21 7 A typical bidirectional connection Master MTB MRB MISO MOSI SCK NSS Slave SRB STB MISO MOSI SCK NSS ...

Page 555: ...the SPIEN bit Note During communication CKPH CKPL MSTMOD PSC 2 0 and LF bits should not be changed SPI basic transmission and reception sequence Transmission sequence After the initialization sequence the SPI is enabled and stays at idle state In master mode the transmission starts when the application writes a data into the transmit buffer In slave mode the transmission starts when SCK clock sign...

Page 556: ...or MRB is different from the reception sequence of full duplex mode In MRU or MRB mode the SPI continuously generates SCK until the SPI is disabled after SPI is enabled So the application should ignore the TBE flag and read out reception buffer in time after the RBNE flag is set otherwise a data overrun fault will occur The slave reception mode SRU or SRB is similar to the reception sequence of fu...

Page 557: ...f TI slave mode D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SCK NSS MOSI MISO sample Td In slave TI mode after the last rising edge of SCK in transfer the slave begins to transmit the LSB bit of the last data byte and after a half bit time the master begins to sample the line To make sure that the master samples the right value the slave should continue to drive this bit after ...

Page 558: ... bit in SPI_QCTL register In Quad SPI mode BDEN BDOEN CRCEN CRCNT FF16 RO and LF bits in SPI_CTL0 register should be kept cleared and MSTMOD should be set to ensure that SPI is in master mode SPIEN PSC CKPL and CKPH bits should be configured as desired There are two operation modes in Quad SPI mode quad write and quad read decided by QRD bit in SPI_QCTL register Quad write operation SPI works in q...

Page 559: ... only to generate SCK clocks so the written data can be any value Once SPI starts transmission it always checks SPIEN and TBE status at the end of a frame and stops when condition is not met So dummy data should always be written into SPI_DATA to generate SCK The operation flow for receiving in quad mode is shown below 1 Configure clock prescaler clock polarity phase etc It based on application re...

Page 560: ...clearing SPIEN bit MTU MTB STU STB Write the last data into SPI_DATA and wait until the TBE flag is set and then wait until the TRANS flag is cleared Disable the SPI by clearing SPIEN bit MRU MRB After getting the second last RBNE flag read out this data and delay for a SCK clock time and then disable the SPI by clearing SPIEN bit Wait until the last RBNE flag is set and read out the last data SRU...

Page 561: ... The CRC calculation uses the polynomial defined in SPI_CRCPOLY register Application can enable the CRC function by setting CRCEN bit in SPI_CTL0 register The CRC calculators continuously calculate CRC for each bit transmitted and received on lines and the calculated CRC values can be read from SPI_TCRC and SPI_RCRC registers To transmit the calculated CRC value application should set the CRCNT bi...

Page 562: ... is 0 When the CONFERR is set the SPIEN bit and the MSTMOD bit are cleared by hardware the SPI is disabled and the device is forced into slave mode The SPIEN bit and MSTMOD bit are write protected until the CONFERR is cleared The CONFERR bit of the slave cannot be set In a multi master configuration the device can be in slave mode with CONFERR bit set which means there might have been a multi mast...

Page 563: ...MCK Master Control Logic Slave Control Logic TX Buffer Shift Register RX Buffer Control Registers 16 bits SYSCLK 16 bits LSB MSB PAD PAD O I O I PAD O I PAD O I APB There are five sub modules to support I2S function including control registers clock generator master control logic slave control logic and shift register All the user configuration registers are implemented in the control registers mo...

Page 564: ...hannel length must be greater than or equal to the data length four packet types are available They are 16 bit data packed in 16 bit frame 16 bit data packed in 32 bit frame 24 bit data packed in 32 bit frame and 32 bit data packed in 32 bit frame The data buffer for transmission and reception is 16 bit wide In the case that the data length is 24 bits or 32 bits two write or read operations to or ...

Page 565: ...d operations to or from the SPI_DATA register are needed to complete the transmission of a frame In transmission mode if a 32 bit data is going to be sent the first data written to the SPI_DATA register should be the higher 16 bits and the second one should be the lower 16 bits In reception mode if a 32 bit data is received the first data read from the SPI_DATA register should be the higher 16 bit...

Page 566: ...CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB When the packet type is 16 bit data packed in 32 bit frame only one write or read operation to or from the SPI_DATA register is needed to complete the transmission of a frame The remaining 16 bits are forced by hardware to 0x0000 to extend the data to 32 bit format MSB justified standard...

Page 567: ...g diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 8 bit 0 MSB Figure 21 29 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 0 I2S_CK I2S_SD 16 bit data frame 1 channel left frame 2 channel right MSB I2S_WS LSB 16 bit 0 MSB Figure 21 30 MSB justified standard timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit da...

Page 568: ...tten to the SPI_DATA register should be a 16 bit data The higher 8 bits of the 16 bit data can be any value and the lower 8 bits should be D 23 16 The second data written to the SPI_DATA register should be D 15 0 In reception mode if a 24 bit data D 23 0 is received the first data read from the SPI_DATA register is a 16 bit data The high 8 bits of this 16 bit data are zeros and the lower 8 bits ar...

Page 569: ...shown below Figure 21 35 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 21 36 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 0 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB LSB frame 1 frame 2 Figure 21 37 PCM standard short frame synchronization mode timing diag...

Page 570: ...CKPL 0 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 Figure 21 42 PCM standard short frame synchronization mode timing diagram DTLEN 00 CHLEN 1 CKPL 1 I2S_CK I2S_SD 16 bit data MSB I2S_WS MSB frame 1 frame 2 16 bit 0 The timing diagrams for each configuration of the long frame synchronization mode are shown below Figure 21 43 PCM standard long frame synchronization mode timing ...

Page 571: ...I2S_CK I2S_SD 32 bits MSB I2S_WS MSB LSB frame 1 frame 2 13 bits Figure 21 47 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 0 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 bit 0 Figure 21 48 PCM standard long frame synchronization mode timing diagram DTLEN 01 CHLEN 1 CKPL 1 I2S_CK I2S_SD 24 bit data MSB I2S_WS MSB frame 1 frame 2 13 bits 8 b...

Page 572: ... OF bit the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register The source clock is the system clock CK_SYS The I2S bitrate can be calculated by the formulas shown in Table 21 7 I2S bitrate calculation formulas Table 21 7 I2S bitrate calculation formulas MCKOEN CHLEN Formula 0 0 I2SCLK DIV 2 OF 0 1 I2SCLK DIV 2 OF 1 0 I2SCLK 8 DIV 2 OF 1 1 I2SCLK 4 DIV 2 OF The relat...

Page 573: ...de The direction of I2S interface signals for each operation mode is shown in the Table 21 9 Direction of I2S interface signals for each operation mode Table 21 9 Direction of I2S interface signals for each operation mode Operation mode I2S_MCK I2S_CK I2S_WS I2S_SD Master transmission Output or NU 1 Output Output Output Master reception Output or NU 1 Output Output Input Slave transmission Input o...

Page 574: ... to select I2S operation mode Configure the DTLEN 1 0 bits and the CHLEN bit to select I2S data format Configure the TBEIE bit the RBNEIE bit the ERRIE bit to enable I2S interrupt optional Configure the DMATEN bit and the DMAREN bit to enable I2S DMA function optional Configure the I2SEN bit to enable I2S No I2S master transmission sequence The TBE flag is used to control the transmission sequence...

Page 575: ...he TBE flag is high and the TRANS flag is low I2S master reception sequence The RBNE flag is used to control the reception sequence As is mentioned before the RBNE flag indicates the receive buffer is not empty and an interrupt will be generated if the RBNEIE bit in the SPI_CTL1 register is set The reception sequence begins immediately when the I2SEN bit in the SPI_I2SCTL register is set At the be...

Page 576: ...ternal master starts the communication The transmission sequence begins when the external master sends the clock and when the I2S_WS signal requests the transfer of data The data has to be written to the SPI_DATA register before the master initiates the communication Software should write the next audio data into SPI_DATA register before the current data finishes Otherwise transmission underrun er...

Page 577: ... register including TBE RBNE TRANS and I2SCH The user can use them to fully monitor the state of the I2S bus Transmit buffer empty flag TBE This bit is set when the transmit buffer is empty the software can write the next data to the transmit buffer by writing the SPI_DATA register Receive buffer not empty flag RBNE This bit is set when receive buffer is not empty which means that one data is rece...

Page 578: ...ror FERR In slave I2S mode the I2S monitors the I2S_WS signal and an error flag will be set if I2S_WS toggles at an unexpected position I2S interrupt events and corresponding enable bits are summed up in the Table 21 10 I2S interrupt Table 21 10 I2S interrupt Interrupt flag Description Clear method Interrupt enable bit TBE Transmit buffer empty Write SPI_DATA register TBEIE RBNE Receive buffer not...

Page 579: ...Bidirectional enable 0 2 line unidirectional transmit mode 1 1 line bidirectional transmit mode The information transfers between the MOSI pin in master and the MISO pin in slave 14 BDOEN Bidirectional transmit output enable When BDEN is set this bit determines the direction of transfer 0 Work in receive only mode 1 Work in transmit only mode 13 CRCEN CRC calculation enable 0 CRC calculation is di...

Page 580: ... SWNSSEN bit is set This bit has no meaning in SPI TI mode 7 LF LSB first mode 0 Transmit MSB first 1 Transmit LSB first This bit has no meaning in SPI TI mode 6 SPIEN SPI enable 0 SPI peripheral is disabled 1 SPI peripheral is enabled 5 3 PSC 2 0 Master clock prescaler selection 000 PCLK 2 100 PCLK 32 001 PCLK 4 101 PCLK 64 010 PCLK 8 110 PCLK 128 011 PCLK 16 111 PCLK 256 PCLK means PCLK2 when us...

Page 581: ...E interrupt is disabled 1 RBNE interrupt is enabled An interrupt is generated when the RBNE bit is set 5 ERRIE Errors interrupt enable 0 Error interrupt is disabled 1 Error interrupt is enabled An interrupt is generated when the CRCERR bit or the CONFERR bit or the RXORERR bit or the TXURERR bit is set 4 TMOD SPI TI mode enable 0 SPI TI Mode Disabled 1 SPI TI Mode Enabled 3 NSSP SPI NSS pulse mode...

Page 582: ...NS RXORERR CONFERR CRCERR TXURERR I2SCH TBE RBNE rc_w0 r r r rc_w0 r r r r Bits Fields Descriptions 31 9 Reserved Must be kept at reset value 8 FERR Format error SPI TI Mode 0 No TI mode format error 1 TI mode format error occurs I2S Mode 0 No I2S format error 1 I2S format error occurs This bit is set by hardware and cleared by writing 0 7 TRANS Transmitting ongoing bit 0 SPI or I2S is idle 1 SPI ...

Page 583: ...un error occurs This bit is set by hardware and cleared by a read operation on the SPI_STAT register This bit is not used in SPI mode 2 I2SCH I2S channel side 0 The next data needs to be transmitted or the data just received is channel left 1 The next data needs to be transmitted or the data just received is channel right This bit is set and cleared by hardware This bit is not used in SPI mode and...

Page 584: ...ission and reception transmit buffer and receive buffer are 16 bit 21 5 5 CRC polynomial register SPI_CRCPOLY Address offset 0x10 Reset value 0x0000 0007 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRCPOLY 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15...

Page 585: ...set value 0x0000 0000 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCRC 15 0 r Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 TCRC 15 0 TX CRC value When the CRCEN bit of SPI_CTL0 is set the hardware computes the CRC value of the transmitted bytes and saves t...

Page 586: ...hen SPI I2S is disabled 10 I2SEN I2S enable 0 I2S is disabled 1 I2S is enabled This bit is not used in SPI mode 9 8 I2SOPMOD 1 0 I2S operation mode 00 Slave transmission mode 01 Slave reception mode 10 Master transmission mode 11 Master reception mode This bit should be configured when I2S is disabled This bit is not used in SPI mode 7 PCMSMOD PCM frame synchronization mode 0 Short frame synchroni...

Page 587: ... 0 CHLEN Channel length 0 16 bits 1 32 bits The channel length must be equal to or greater than the data length This bit should be configured when I2S mode is disabled This bit is not used in SPI mode 21 5 9 I2S clock prescaler register SPI_I2SPSC Address offset 0x20 Reset value 0x0000 0002 This register can be accessed by half word 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 1...

Page 588: ...ord 16 bit or word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved IO23_DR V QRD QMOD rw rw rw Bits Fields Descriptions 31 3 Reserved Must be kept at reset value 2 IO23_DRV Drive IO2 and IO3 enable 0 IO2 and IO3 are not driven in single wire mode 1 IO2 and IO3 are driven to high in single wire mode This bit is only available in SPI0 1 ...

Page 589: ...GD32A50x User Manual 589 This bit is only available in SPI0 ...

Page 590: ...ing together with a PWM output of a timer and the DAC It blanking function can be used for false overcurrent detection in motor control applications 22 2 Characteristic Rail to rail comparators Configurable hysteresis Configurable speed and consumption Comparator has configurable analog input source DAC Multiplexed I O pins The whole or sub multiple values of internal reference voltage Outputs wit...

Page 591: ...to work even in deep sleep mode the polarity selection logic and the output redirection to the port work independently from PCLK The CMP output can be redirected internally and externally simultaneously The CMP output are internally connected to the extended interrupts and events controller CMP has its own EXTI line and can generate either interrupts or events The same mechanism is used to exit fr...

Page 592: ...eset This write protection function is useful in some applications such as thermal protection and over current protection 22 3 4 CMP power mode For a given application there is a trade off between the CMP power consumption versus propagation delay which is adjusted by configuring bits PM 1 0 in CMP_CS register The CMP works fastest with highest power consumption when PM 2 b00 while works slowest w...

Page 593: ..._OUT CMP_IM Vhyst CMP_IM CMP_IP 22 3 6 CMP interrupt The CMP output is connected to the EXTI and the EXTI line is exclusive to CMP With this function CMP can generate either interrupt or event which could be used to exit from sleep modes or deep sleep modes ...

Page 594: ...ts are read write 1 CMP_CS bits are read only 30 OT CMP output This is a copy of CMP output state which is read only 0 Non inverting input below inverting input and the output is low 1 Non inverting input above inverting input and the output is high 29 24 Reserved Must be kept at reset value 23 SEN Voltage scaler enable bit This bit is set and cleared by software This bit enable the outputs of the...

Page 595: ...on These bits are used to select the destination of the CMP output 00 no selection 01 TIMER0 channel0 input capture 10 TIMER7 channel0 input capture 11 Reserved Note It is recommended to enable CMP first and then configure the timer channel when using TIMER0 7 channel0 to capture the output signal of the comparator 12 10 PSEL 2 0 CMP_IP input selection These bits are used to select the source conn...

Page 596: ...l source connected to the CMP_IM input of the CMP 000 PC11 001 PC10 010 PB8 011 PA0 100 PA3 101 PA4 110 PA5 111 PA6 3 2 PM 1 0 CMP mode These bits are used to control the operating mode of the CMP adjust the speed consumption 00 High speed full power 01 10 Medium speed medium power 11 Low speed low power 1 Reserved Must be kept at reset value 0 EN CMP enable 0 CMP disabled 1 CMP enabled ...

Page 597: ...98 1 2015 standard Supports CAN FD frame with up to 64 data bytes baudrate up to 8 Mbit s Supports CAN classical frame with up to 8 data bytes baudrate up to 1 Mbit s Supports time stamp based on 16 bit free running counter Supports transmitter delay compensation for CAN FD frames at faster data rates Maskable interrupts Supports four communication mode normal mode Inactive mode Loopback and silen...

Page 598: ...CAN_RX Mailbox System Control Shift in out Protocol Controller CAN_sleep Rx matching MAC PCS As shown in Figure 23 1 CAN module block diagram CAN module includes three main parts The Protocol controller The Protocol controller manages the communication on the CAN bus including MAC Media Access Control Bit stuffing de stuffing Stuff bit count for FD Frames Add CRC Construction of MAC frame ACK chec...

Page 599: ...B bus 23 3 1 Mailbox descriptor The mailbox descriptor shown in Table 23 1 Mailbox descriptor with 64 byte payload can be used for both extended 29 bit identifier and standard 11 bit identifier frames Each mailbox is formed by 16 24 40 or 72 bytes depending on the data bytes allocation for the message payload 8 16 32 or 64 data bytes respectively The memory area from offset 0x80 to 0x27F is used b...

Page 600: ...d with the value received on the CAN bus 28 Reserved Must be kept at rest value 27 24 CODE 3 0 Mailbox Code CODE This bit field can be accessed by the CPU and by the CAN module as part of the mailbox matching and arbitration process The encoding is shown in Table 23 3 Mailbox Rx CODE and Table 23 4 Mailbox Tx CODE 23 Reserved Must be kept at rest value 22 SRR Substitute remote request This bit is ...

Page 601: ...0 Data length code in bytes This bit field is the length in bytes of the Rx or Tx payload For reception Rx mailbox no need to write this bit field they are written by the CAN module with the DLC field of the received frame For transmission Tx mailbox this bit field is written by the CPU with value of the frame to be transmitted When RTR is 1 the frame to be transmitted is a remote request frame an...

Page 602: ... 0 The code is automatically changed to TANSWER 1 This code is ignored during matching and arbitration process CODE 0 1 BUSY 4 FULL Indicates that the mailbox is being updated OVERRUN 1 Serviced Mailbox was serviced by CPU read and was unlocked by reading CAN_TIMER register or other mailbox 2 Remote Request Frame Stored bit refer to Control register 2 CAN_CTL2 3 A mailbox with CODE 0b1010 should n...

Page 603: ...15 14 13 12 11 rw 9 8 7 6 5 4 3 2 1 0 ID_EXD 15 0 rw Bits Fields Descriptions 31 29 PRIO 2 0 Local priority This bit field is only used when LAPRIOEN bit in CAN_CTL0 register is set This bit filed is only used for Tx mailboxes while these bits are not transmitted they are appended to the regular ID to define the transmission priority 28 18 ID_STD 10 0 Identifier for standard frame In standard fram...

Page 604: ... the complete mailbox descriptor length with 8 16 32 or 64 data bytes When Rx FIFO is enabled CAN FD mode disabled data field is 8 byte length the dedicated RAM space is occupied by both mailboxes and FIFO so uniformly count the descriptor number by a mailbox descriptor length with 8 data bytes then the mailbox number is the descriptor number which is occupied by mailbox Mailbox size for CAN FD Wh...

Page 605: ...5 0 FDES1 Reserved ID_STD 10 0 ID_EXD 17 0 FDES2 DATA_0 7 0 DATA_1 7 0 DATA_2 7 0 DATA_3 7 0 FDES3 DATA_4 7 0 DATA_5 7 0 DATA_6 7 0 DATA_7 7 0 0x90 0xDC Reserved FDES4 ID filter table element 0 FDES1 07 ID filter table element 103 FDES0 Rx FIFO descriptor word 0 Address offset 0x80 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDFMN 8 0 SRR IDE RTR DLC 3 0 r r r r r 15 14 13 12 11 10 9 8 7 6 5 4...

Page 606: ...scriptor word 1 Address offset 0x84 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved ID_STD 10 0 ID_EXD 17 16 r r 15 14 13 12 11 rw 9 8 7 6 5 4 3 2 1 0 ID_EXD 15 0 r Bits Fields Descriptions 31 29 Reserved Must be kept at rest value 28 18 ID_STD 10 0 Identifier for standard frame In standard frame format only these 11 most significant bits 28 to 18 are used for frame identification The 18 ...

Page 607: ...8 7 6 5 4 3 2 1 0 DATA_6 7 0 DATA_7 7 0 r r Bits Fields Descriptions 31 24 DATA_4 7 0 Data byte 4 Refer to DATA_7 7 0 descriptions 23 16 DATA_5 7 0 Data byte 5 Refer to DATA_7 7 0 descriptions 15 8 DATA_6 7 0 Data byte 6 Refer to DATA_7 7 0 descriptions 7 0 DATA_7 7 0 Data byte 7 Up to 8 bytes can be used for a data frame depending on the DLC value of the mailbox FD frames is not supported to rece...

Page 608: ...hen matches 0 Extended frames are rejected and standard frames can be stored 1 Extended frames can be stored and standard frames are rejected 29 Reserved Must be kept at rest value 28 1 ID_STD_A 10 0 ID_EXD_A 28 0 ID in format A This bit field specifies one full standard ID standard or extended for Rx FIFO matching process If IDE_A is 0 the 18 to 28 bits are used for standard ID and the rest bits ...

Page 609: ...red with the 14 most significant bits of the received ID 15 RTR_B1 Remote frame 1 for format B Refer to RTR_B0 descriptions 14 IDE_B1 ID Extended frame 1 for format B Refer to IDE_B0 descriptions 13 0 ID_STD_B_1 10 0 ID_EXD_B_1 13 0 ID for frame 1 in format B Refer to ID_STD_B_0 10 0 ID_EXD_B_0 13 0 descriptions Format C mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ID_C_0 7 0 ID_C_1 7 0 rw...

Page 610: ...hed A pending shift in does not prevent entering Inactive mode 3 The Tx pin is driven as 1 recessive 4 Stop the prescaler 5 Enable write access to the CAN_ERR0 register which is read only in other modes 6 Set NRDY bit and INAS bit in CAN_CTL0 register When Inactive mode is entered INAS bit in CAN_CTL0 register is set to 1 by CAN In Inactive mode neither transmission nor reception is performed and ...

Page 611: ...acknowledged will lead to a bit dominant error flag without changing the RECNT 7 0 or REFCNT 7 0 in CAN_ERR0 register 23 3 4 Power saving modes The CAN interface has two power saving modes CAN_Disable mode Pretended Networking mode In these two power saving modes the dedicated RAM and the registers in SRAM can not be accessed CAN_Disable mode The CAN module is enabled or disabled by configuring th...

Page 612: ...to filter messages The matching arbitration shift in and shift out processes are not performed in Pretended Networking mode To exit from Pretended Networking mode the following method can meet When a wakeup event is detected and a wake up interrupt is occured Clear LPS bit and PNS bit in CAN_CTL0 register Clear LPS bit and PNS bit in CAN_CTL0 register If exiting from Pretended Networking mode is r...

Page 613: ...MESTAMP field is automatically updated with the value of the free running counter the CRC registers CAN_CRCC and CAN_CRCCFD are updated and the corresponding flag MSx in the CAN_STAT register is set if the interrupt enable bit MIEx in CAN_INTEN register is set an interrupt will be generated Arbitration process When more than one Tx mailbox is pending the arbitration process which searching from th...

Page 614: ...ble 23 7 Mailbox arbitration value 32 bit when local priority disabled and Table 23 8 Mailbox arbitration value 35 bit when local priority enabled among all Tx mailboxes If more than one mailboxes have equivalent arbitration values the mailbox with the lowest number is the arbitration winner When LAPRIOEN bit in CAN_CTL0 register is set to 1 the local priority is disabled the bits participate in t...

Page 615: ...in CAN_CTL0 register is set The write access to MDES0 word of the corresponding mailbox is recoverd when matching one of the following situations After the mailbox is transmitted and the corresponding flag MSx in the CAN_STAT register is cleared by the CPU CAN node enters Inactive mode or Bus Off state CAN node loses the bus arbitration or there is an error during the transmission The shift out pr...

Page 616: ...e failed to be transmitted Lose the bus arbitration There is an error during the transmission Enter Bus Off state There is an overload frame Tx mailbox inactivation The way to inactivate a Tx mailbox Write the CODE field of the Tx mailbox MDES0 with ABORT This is the recommended way for inactivation which will not cause the unknown transmission This operation must be done when MST bit in the CAN_C...

Page 617: ... the mailbox MDES0 word and poll until the BUSY bit in CODE field is 0 When the BUSY bit is 0 the read operation of the mailbox will lock the mailbox so that to prevent the mailbox being overwritten 3 Read the contents of the mailbox 4 Clear the corresponding flag MSx in the CAN_STAT register 5 Read CAN_TIMER register to unlock the mailbox Rx mailbox locking A locking mechanism is only applied for...

Page 618: ...pt will be generated while if DMAEN bit in CAN_CTL0 register is set the MS5_RFNE flag will generate the DMA request and no Rx FIFO interrupt is generated To service read Rx FIFO by CPU the recommended steps are shown as below 1 Poll the flag MS5_RFNE in the CAN_STAT register to be set or by the interrupt when MIE5 bit in CAN_INTEN register is set 2 Read the Rx FIFO FDES0 FDES3 words and if needed ...

Page 619: ...ctive mode must be performed to clear the Rx FIFO contents The act of clearing FIFO will clear MS5_RFNE bit in the CAN_STAT register and cancel the DMA request Clear FIFO when Rx FIFO is enabled RFEN bit in CAN_CTL0 register is 1 set MS0 bit in the CAN_STAT register to 1 in Inactive mode will clear the Rx FIFO contents while the Rx FIFO flags will not be cleared except in DMA mode thus before clea...

Page 620: ...then matching is processed on Rx FIFO In this case if the Rx FIFO is matched but it is full it will leads to Rx FIFO overflow while if the Rx FIFO is not matched no matter it is full or not the message will not be received If RFO bit is set to 0 matching process starts from Rx FIFO to Rx mailbox If the Rx FIFO matches the searching conditions and is not full then the Rx FIFO is the matching winner...

Page 621: ...N_CTL2 register is 0 it means the IDE field will be compared and RTR field will not be compared regardless of bit 30 and bit 31 in related filter register The ID field will be compared using bit 0 to bit 28 filter data configurations in related filter register When IDERTR_RMF bit in CAN_CTL2 register is 1 it means all the IDE RTR and ID fields will be compared using bit 0 to bit 28 bit 30 bit 31 f...

Page 622: ...hing FS 1 0 in CAN_CTL0 register IDE RTR ID 0 Filtered 1 Filtered 2 Never Filtered 3 Not match 1 1 Not match All frames are rejected Shift in The shift in process is the copy operation of the content from a Rx shift buffer an internal mailbox descriptor to a Rx mailbox or Rx FIFO that matched it When there is a matching descriptor found in the FIFO or in the Rx mailboxes a shift in process will be...

Page 623: ...ually When Rx FIFO is enabled If RPFQEN bit in CAN_CTL0 register is 0 then CAN_RMPUBF is used for all mailboxes CAN_RFIFOPUBF and CAN_RFIFOMPFx x 0 31 are used for all the Rx FIFO ID filter table elements and the value of these registers must be all the same If RPFQEN bit in CAN_CTL0 register is 1 then CAN_RFIFOMPFx x 0 31 is used for the Rx FIFO ID filter table elements defined by RFFN 3 0 bits i...

Page 624: ...nd a dedicated enable bit in CAN_PN_CTL0 register The relationship is described in the Table 23 11 Interrupt events An wakeup interrupt can be generated when any type of the wakeup interrupt event occurs and enabled Wakeup timeout event When CAN reaches the timeout value a wakeup timeout event will occur The timeout is configured by WTO 15 0 bits in CAN_PN_TO register Note Even if the timeout valu...

Page 625: ...tching When IDFT 1 0 bit field in CAN_PN_CTL0 register is configured to 0 it means the ID field of a matched message is the same as the configured expected ID field in CAN_PN_EID0 register using filter data in CAN_PN_IFEID1 register When IDFT 1 0 bit field in CAN_PN_CTL0 register is configured to 1 it means the ID field of a matched message is larger than or equal to the configured expected ID fie...

Page 626: ...8 bytes then in DATA field matching the data that matching with the expected data is the received DATA field plus the padding value zeros 23 3 8 CAN FD operation Both ISO CAN FD ISO11898 1 specification and non ISO Bosch CAN FD Specification V1 0 CAN FD protocols are supported but they are incompatible with each other so select the protocol by ISO bit in CAN_CTL2 register In comparison to the non ...

Page 627: ... mailbox and ERRSI 1 0 bits in CAN_ERR1 register If ESI field in MDES0 is 0 it will transmit the dominant bit by error active nodes and transmit the recessive bit by error passive nodes according to ERRSI 1 0 bits in CAN_ERR1 register If ESI field in MDES0 is 1 it will transmit ESI field in MDES0 word CAN FD CRC Different CRC polynomials are used for different frame formats results in a Hamming di...

Page 628: ...or CAN classical format frames stuff bits are not included Resynchronization Resynchronization and hard synchronization occur in CAN FD frames in the same way as in CAN classical frames Resynchronization is not performed in transmitting the CAN FD data phase Transmitter delay compensation The transmitter delay compensation is used for the data phase of CAN FD frames with BRS set for the reason tha...

Page 629: ...nsmitter delay then TDCS bit in CAN_FDCTL register will be set The implementation shall be able to compensate transmitter delays of at least two data bit times 23 3 9 Errors and states Transmit Error Counter TECNT 7 0 bits in CAN_ERR0 register and Receive Error Counter RECNT 7 0 bits in the CAN_ERR0 register take into account all errors in both CAN FD and non FD messages which get incremented or d...

Page 630: ...covery sequence specified in the CAN standard 128 occurrences of 11 consecutive recessive bits monitored on CAN RX When TECNT 7 0 in CAN_ERR0 register reaches 128 ERRSI 1 0 in CAN_ERR1 register is updated to 0 error active state and both TECNT 7 0 and RECNT 7 0 in CAN_ERR0 register are reset to 0 Depending on ABORDIS bit in CAN_CTL1 register CAN will recover from Bus off automatically or remain in...

Page 631: ...s set an error interrupt will be generated If at least one of the error flags BRFERR BDFERR CRCFERR FMFERR and STFFERR bit in CAN_ERR1 register is set ERRFSF bit in CAN_ERR1 register will be set If ERRFSIE bit in CAN_CTL2 register is set an error interrupt will be generated for errors detected in CAN FD frame data phase with BRS bit set Acknowledge error If there is only one node operating then it...

Page 632: ...uration should programmed no less than 2 time quanta Note The bit time configuration ranges must be in compliance with the CAN Protocol standard ISO 11898 1 CAN bit time is shown as in the Figure 23 3 CAN bit time Figure 23 3 CAN bit time Sync segment Propagation segment Phase buffer segment 1 Phase buffer segment2 CAN Bit Time CAN protocol SYNG_SEG BIT SEGMENT 1 BS1 BIT SEGMENT 2 BS2 CAN tSYNC_SE...

Page 633: ...from the APB2 clock The clock of Protocol controller CANCLK can be configured by CANxSEL 1 0 bit in RCU_CFG2 register to derive from oscillator clock or APB2 clock or APB2 clock devided by 2 or IRC8M internal clock The CAN calculates its baudrate as follows BaudRate 1 CAN Bit Time 23 7 CAN Bit Time tSYNC_SEG tPTS tPBS1 tPBS2 23 8 with tSYNC_SEG 1 tq 23 9 tPTS NPTS 1 tq or tPTS NDPTS tq 23 10 tPBS1...

Page 634: ... clock source When ITSRC bit in CAN_CTL2 register is 1 the internal counter clock source is selected to TRIGSEL output CANx_EX_TIME_TICK while the frequency must be synchronous to CANCLK When ITSRC bit in CAN_CTL2 register is 0 the internal counter clock source is selected to the CAN baudrate it increments by one for each bit that is received or transmitted When there is no message on the bus it i...

Page 635: ...0 Rx error warning RWERRIF RWERRIE Wakeup match WMS CAN_PN_STAT WMIE CAN_PN_CTL0 Wakeup timeout WTOS WTOIE Mailbox successful transmission or reception All bits CAN_STAT All bits RFEN 0 CAN_INTE N CAN_CTL0 MSx MIEx RFEN 1 Rx FIFO not empty MS5_RFNE MIE5 RFEN 1 DMAEN 0 Rx FIFO warning MS6_RFW MIE6 Rx FIFO overflow MS7_RFO MIE7 23 4 Example for a typical configuration flow of CAN After power on rese...

Page 636: ...AN_CTL2 register if needed 3 Enable transmission abort function for Tx mailbox descriptor configuration by MST bit in CAN_CTL0 register Configure the control parameters for reception 1 Choose whether use Rx FIFO and Rx FIFO DMA for reception or not by RFEN bit and DMAEN bit in CAN_CTL0 register 2 Configure Rx private filter Rx mailbox queue feature by RPFQEN bit in CAN_CTL0 register 3 Configure re...

Page 637: ...he Rx mailbox descriptors if Rx FIFO is enabled also initialize the Rx FIFO descriptors including the ID filter table elements If Pretended Networking mode is required set PNEN bit and PNMOD bit in CAN_CTL0 register and configure the necessary registers for wakeup Exit Inactive mode Clear HALT bit in CAN_CTL0 register to exit Inactive mode and CAN starts to synchronize to the CAN bus ...

Page 638: ...ved SWRST INAS Reserved WERREN LPS PNEN PNS SRDIS RPFQEN rw rw rw rw r rw r rw r rw r rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DMAEN PNMOD LAPRIOE N MST FDEN Reserved FS 1 0 Reserved MSZ 4 0 rw rw rw rw rw rw rw Bits Fields Descriptions 31 CANDIS CAN disable 0 Enable CAN module 1 Disable CAN module 30 INAMOD Inactive mode enable 0 Disable Inactive mode 1 Enable Inactive mode 29 RFEN Rx FIFO ena...

Page 639: ...RWERRF bit in CAN_ERR1 register respectively 0 Disable Tx and Rx error warining 1 Enable Tx and Rx error warining 20 LPS Low power state 0 Not in low power state 1 In low power state 19 PNEN Pretended Networking mode enable 0 Disable Pretended Networking mode 1 Enable Pretended Networking mode 18 PNS Pretended Networking state 0 Not in Pretended Networking state 1 In Pretended Networking state 17 ...

Page 640: ...Format C Four partial 8 bit IDs standard and extended per ID filter table element 11 Format D All frames rejected 7 5 Reserved Must be kept at reset value 4 0 MSZ 4 0 Memory size This bit field defines the maximum size of memory for message transmission and reception The size is counted in uint of 4 words equals to the size of a mailbox descriptor with 8 byte data including mailbox and Rx FIFO Bef...

Page 641: ... communication mode Note In this mode SRDIS bit in CAN_CTL0 register and TDCEN in CAN_FDCTL register cannot be set 11 TWERRIE Tx error warning interrupt enable This bit can be written only when WERREN in CAN_CTL0 register is 1 This bit is read as zero when WERREN in CAN_CTL0 register is 0 0 Disable Tx error warning interrupt 1 Enable Tx error warning interrupt 10 RWERRIE Rx error warning interrupt...

Page 642: ...eserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 CNT 15 0 Counter value This bit field contains the internal counter value used for timestamp generation 23 5 4 Receive mailbox public filter register CAN_RMPUBF Address offset 0x10 Reset value 0xXXXX XXXX This register is located in RAM All bits of this register should...

Page 643: ...y word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 REFCNT 7 0 TEFCNT 7 0 rw0 rw0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RECNT 7 0 TECNT 7 0 rw rw Bits Fields Descriptions 31 24 REFCNT 7 0 Receive error counter for data phase of FD frames with BRS bit set This bit field can only be written as zero in Inactive mode 23 16 TEFCNT 7 0 Transmit error count for the data phase of FD frames with ...

Page 644: ...ence 1 A CRC error occurred 27 FMFERR Form error in data phase of FD frames with the BRS bit set 0 No error occurrence 1 A form error occurred 26 STFFERR Stuff error in data phase of FD frames with the BRS bit set 0 No error occurrence 1 A stuff error occurred 25 22 Reserved Must be kept at reset value 21 ERROVR Error overrun This bit indicates that an error condition occurred when any error flag ...

Page 645: ...cessive is received as dominant 14 BDERR Bit dominant error for all format frames This bit is updated when exiting from Pretended Networking mode 0 No error occurrence 1 At least one bit sent as dominant is received as recessive 13 ACKERR ACK error This bit is updated when exiting from Pretended Networking mode 0 No error occurrence 1 An ACK error occurred 12 CRCERR CRC error This bit is updated w...

Page 646: ... one CAN bit time and then changes to 0b01 to reflect Monitor mode state 00 Error active 01 Error passive 1x Bus off 3 RS Receiving state 0 CAN is not working in receiving state 1 CAN is working in receiving state 2 BOF Bus off flag 0 No event occurrence 1 In Bus off state 1 ERRSF Error summary flag This bit is logical ORed by the following bits CAN_ERR1 15 Bit recessive error CAN_ERR1 14 Bit domi...

Page 647: ... bit in CAN_CTL0 register This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MS31 MS30 MS29 MS28 MS27 MS26 MS25 MS24 MS23 MS22 MS21 MS20 MS19 MS18 MS17 MS16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MS15 MS14 MS13 MS12 MS11 MS10 MS9 MS8 MS7_RFO MS6_RFW MS5_RFNE M...

Page 648: ...essful transmission or reception has occurred in the mailbox descriptor 1 when Rx FIFO is disabled Reserved when Rx FIFO is enabled 1 A successful transmission or reception has occurred in the mailbox descriptor 1 when Rx FIFO is disabled Reserved when Rx FIFO is enabled 0 MS0_RFC Mailbox 0 state Clear Rx FIFO bit 0 No successful transmission or reception has occurred in the mailbox descriptor 0 w...

Page 649: ...x descriptor 0 9 Mailbox 10 31 0002 24 Mailbox descriptor 0 11 Mailbox 12 31 0003 32 Mailbox descriptor 0 13 Mailbox 14 31 0004 40 Mailbox descriptor 0 15 Mailbox 16 31 0005 48 Mailbox descriptor 0 17 Mailbox 18 31 0006 56 Mailbox descriptor 0 19 Mailbox 20 31 0007 64 Mailbox descriptor 0 21 Mailbox 22 31 0008 72 Mailbox descriptor 0 23 Mailbox 24 31 0009 80 Mailbox descriptor 0 25 Mailbox 26 31 0...

Page 650: ...y filter data configurations in related filter register 15 ITSRC Internal counter source 0 CAN baudrate 1 External trigger CANx_EX_TIME_TICK from TRIGSEL output 14 PREEN Protocol exception detection enable by CAN standard 0 Disable protocol exception detection 1 Enable protocol exception detection 13 Reserved Must be kept at reset value 12 ISO ISO CAN FD 0 Non ISO CAN FD protocol operation is appl...

Page 651: ...nly because they are blocked by hardware in other modes This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FFD31 FFD30 FFD29 FFD27 FFD27 FFD26 FFD25 FFD24 FFD23 FFD22 FFD21 FFD20 FFD19 FFD18 FFD17 FFD16 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FFD15 FFD14 FFD13 FFD12 FFD11 FFD10 FFD9 FFD8 FFD7 FFD6 FFD5 FFD4 ...

Page 652: ...ffset 0x50 Reset value 0x0100 0000 All bits of this register should be configured in Inactive mode only because they are blocked by hardware in other modes This register is not affected by software reset bit SWRST in CAN_CTL0 register This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved BAUDPSC 9 0 SJW 4 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 ...

Page 653: ...rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMFD15 FMFD14 FMFD13 FMFD12 FMFD11 FMFD10 FMFD9 FMFD8 FMFD7 FMFD6 FMFD5 FMFD4 FMFD3 FMFD2 FMFD1 FMFD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits Fields Descriptions 31 0 FMFDx FIFO mailbox filter data If used as mailbox filters refer to the MFDx bits in CAN_RMPUBF register If used as Rx FIFO filters refer to ...

Page 654: ...ter than or equal to the expected data low threshold are matched 10 Messages with DATA field smaller than or equal to the expected data high threshold are matched 11 Messages with DATA field greater than or equal to the expected data low threshold and smaller than or equal to the expected data high threshold are matched 3 2 IDFT 1 0 ID field filtering type in Pretended Networking mode 00 Only mess...

Page 655: ... 19 18 17 16 Reserved 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 WTO 15 0 rw Bits Fields Descriptions 31 16 Reserved Must be kept at reset value 15 0 WTO 15 0 Wakeup timeout The timeout is counted by step of 64 times the CAN Bit Time Wakeup timeout is default disabled 23 5 17 Pretended Networking mode status register CAN_PN_STAT Address offset 0xB08 Reset value 0x0000 0080 This register has to be acces...

Page 656: ...6 0 Reserved Must be kept at reset value 23 5 18 Pretended Networking mode expected identifier 0 register CAN_PN_EID0 Address offset 0xB0C Reset value 0x0000 0000 All bits of this register should be configured in Inactive mode only because they are blocked by hardware in other modes This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved EIDE ERTR E...

Page 657: ...25 24 23 22 21 20 19 18 17 16 Reserved DLCELT 3 0 rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved DLCEHT 3 0 rw Bits Fields Descriptions 31 20 Reserved Must be kept at reset value 19 16 DLCELT 3 0 DLC expected low threshold in Pretended Networking mode 15 4 Reserved Must be kept at reset value 3 0 DLCEHT 3 0 DLC expected high threshold in Pretended Networking mode 23 5 20 Pretended Networking mo...

Page 658: ...ng mode expected data low 1 register CAN_PN_EDL1 Address offset 0xB18 Reset value 0x0000 0000 All bits of this register should be configured in Inactive mode only because they are blocked by hardware in other modes This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DB4ELT 7 0 DB5ELT 7 0 rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DB6ELT 7 0 DB7ELT 7 0 r...

Page 659: ...0 The bit is don t care 1 The bit is checked 29 RTRFD RTR filter data in Pretended Networking mode 0 The bit is don t care 1 The bit is checked 28 0 IDFD_EHT 28 0 ID filter data ID expected high threshold in Pretended Networking mode ID filter data when IDFT 1 0 bit field in CAN_PN_CTL0 register is 0 0 The bit is don t care 1 The bit is checked ID expected high threshold when IDFT 1 0 bit field is...

Page 660: ...g mode Refer to DB3FD_EHT 7 0 descriptions 7 0 DB3FD_EHT 7 0 Data byte 3 filter data Data byte 2 expected high threshold in Pretended Networking mode Data byte 3 filter data when DATAFT 1 0 bit field in CAN_PN_CTL0 register is 0 0 The bit is don t care 1 The bit is checked Data byte 3 expected high threshold when DATAFT 1 0 bit field is 3 Bits reserved when DATAFT 1 0 bit field is 1 or 2 23 5 24 P...

Page 661: ... byte 7 filter data Data byte 7 expected high threshold in Pretended Networking mode Refer to DB3FD_EHT 7 0 descriptions 23 5 25 Pretended Networking mode received wakeup mailbox x control status information register CAN_PN_RWMxCS x 0 3 Address offset 0xB40 16 x Reset value 0x0000 0000 This register has to be accessed by word 32 bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved RSRR RID...

Page 662: ...8 7 6 5 4 3 2 1 0 RID 15 0 r Bits Fields Descriptions 31 29 Reserved Must be kept at reset value 28 0 RID 28 16 Received ID bits For extended frame format all 29 bits are used for ID storage For standard frame format bits 18 to 28 are used for ID storage 23 5 27 Pretended Networking mode received wakeup mailbox x data 0 register CAN_PN_RWMxD0 x 0 3 Address offset 0xB48 16 x Reset value 0x0000 0000...

Page 663: ...scriptions 31 24 RDB4 7 0 Received data byte 4 23 16 RDB5 7 0 Received data byte 5 15 8 RDB6 7 0 Received data byte 6 7 0 RDB7 7 0 Received data byte 7 23 5 29 FD control register CAN_FDCTL Address offset 0xC00 Reset value 0x8000 0101 Bits 17 16 15 12 8 of this register should be configured in Inactive mode only because they are blocked by hardware in other modes This register is not affected by s...

Page 664: ...ion range it is unable to compensate the transmitter delay for bit check 0 Transmitter delay is in compensation range 1 Transmitter delay is out of compensation range 13 Reserved Must be kept at reset value 12 8 TDCO 4 0 Transmitter delay compensation offset These bits are set to the transmitter delay compensation offset value which defines the distance between the measured delay from CANTX to CAN...

Page 665: ... quantum DSJW 2 0 1 15 Reserved Must be kept at reset value 14 10 DPTS 4 0 Propagation time segment for data bit time Propagation time segment time quantum DPTS 4 0 9 8 Reserved Must be kept at reset value 7 5 DPBS1 2 0 Phase buffer segment 1 for data bit time Phase buffer segment 1 time quantum DPBS1 2 0 1 4 3 Reserved Must be kept at reset value 2 0 DPBS2 2 0 Phase buffer segment 2 for data bit ...

Page 666: ...transmits the CRCTCI 20 0 value for both classical and FD frames 23 21 Reserved Must be kept at reset value 20 0 CRCTCI 20 0 Transmitted CRC value for classical and ISO non ISO FD frames For CRC_15 bits 0 to 14 are used the other bits are zeros and the value is the same as the value of CRCTC 14 0 in CAN_CRCC register For CRC_17 bits 0 to 16 are used the other bits are zeros For CRC_21 all 21 bits ...

Page 667: ... as set this bit to 1 Writing 0 has no effect on the bit value read clear by read rc_r Software can read this bit Reading this bit automatically clears it to 0 Writing 0 has no effect on the bit value 24 2 List of terms Table 24 2 List of terms Glossary Descriptions Word Data of 32 bit length Half word Data of 16 bit length Byte Data of 8 bit length IAP in application programming Writing 0 has no ...

Page 668: ...GD32A50x User Manual 668 24 3 Available peripherals For availability of peripherals and their number across all MCU series types refer to the corresponding device data datasheet ...

Page 669: ...GD32A50x User Manual 669 25 Revision history Table 25 1 Revision history Revision No Description Date 1 0 Initial Release Sep 15 2022 ...

Page 670: ...y business industrial personal and or household applications only The Products are not designed intended or authorized for use as components in systems designed or intended for the operation of weapons weapons systems nuclear installations atomic energy control instruments combustion control instruments airplane or spaceship instruments transportation instruments traffic signal instruments life su...

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