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Fujitsu MHV2040BH, Product Manual

The Fujitsu MHV2040BH Maintenance Manual is a comprehensive guide that assists users in effectively troubleshooting and maintaining their MHV2040BH hard drive. This essential manual is available for free download at manualshive.com, ensuring you have the necessary resources to keep your device running smoothly.

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Interface 

 

5-18 

C141-E224 

The host system uses the Register - Host to Device FIS when information in the 
Register Block is transferred from the host system to the device.  This is the 
mechanism for issuing the ATA command from the host system to the device. 

C -  To update the Command field, "1" would be set in this field; and to update 
the Device Control field, "0" would be set in the field. 

If both C = 1 and SRST = 1 are set, operation is not guaranteed. 

5.2.3.3  Register - Device to Host 

The Register - Device to Host FIS has the following layout: 

 

3
1 

3
0 

2
9 

2
8 

2
7 

2
6 

2
5 

2
4 

2
3 

2
2 

2
1 

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

9 8 7 6 5 4 3 2 1 0

Error 

Status 

R I R Reserved (0)

FIS Type (34h) 

0 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Device 

LBA High 

LBA Mid 

LBA Low 

1 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved (0) 

LBA High (exp) 

LBA Mid (exp) 

LBA Low (exp) (0) 

2 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved (0) 

Reserved (0) 

Sector Count (exp) 

Sector Count 

3 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reserved (0) 

Reserved (0) 

Reserved (0) 

Reserved (0) 

4 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.5  Register - Device to Host FIS layout 

The Register - Device to Host FIS is used when information concerning the Shadow 
Register Block in the host adapter is updated.  This FIS indicates that the device has 
completed a command operation.  Furthermore, this is a mechanism for changing 
information concerning the Shadow Register Block of the host adapter. 

I -  If this bit is set, an interrupt request is issued to the host system. 

5.2.3.4  DMA Active - Device to Host 

The DMA Active - Device to Host FIS has the following layout: 

 

3
1 

3
0 

2
9 

2
8 

2
7 

2
6 

2
5 

2
4 

2
3 

2
2 

2
1 

2
0

1
9

1
8

1
7

1
6

1
5

1
4

1
3

1
2

1
1

1
0

9 8 7 6 5 4 3 2 1 0

Reserved (0) 

Reserved (0) 

R R R Reserved (0)

FIS Type (39h) 

0 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 5.6  DMA Active - Device to Host FIS layout 

Summary of Contents for MHV2040BH

Page 1: ...C141 E224 02EN MHV2120BH MHV2100BH MHV2080BH MHV2060BH MHV2040BH DISK DRIVES PRODUCT MANUAL ...

Page 2: ...ncidental or consequential damages arising therefrom FUJITSU DISCLAIMS ALL WARRANTIES REGARDING THE INFORMATION CONTAINED HEREIN WHETHER EXPRESSED IMPLIED OR STATUTORY FUJITSU reserves the right to make changes to any products described herein without further notice and without obligation This product is designed and manufactured for use in standard applications such as office work personal device...

Page 3: ...ire manual Added Addition of MHV2120BH model Section 5 2 3 8 5 2 3 9 Added Addition of description for PIO Setup Device to Host and Set Device Bits Device to Host 02 2005 11 10 Section 5 3 Added Addition of UNLOAD IMMEDIATE command 1 Section s with asterisk refer to the previous edition when those were deleted ...

Page 4: ...This page is intentionally left blank ...

Page 5: ...ce Overview This chapter gives an overview of the disk drive and describes their features CHAPTER 2 Device Configuration This chapter describes the internal configurations of the disk drive and the configuration of the systems in which they operate CHAPTER 3 Installation Conditions This chapter describes the external dimensions installation conditions and switch settings of the disk drive CHAPTER ...

Page 6: ...t signal is centered followed below by the indented message A wider line space precedes and follows the alert message to show where the alert message begins and ends The following is an example Example Data corruption Avoid mounting the disk drive near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields The main alert messages in the...

Page 7: ...at the back of this manual and forward it to the address described in the sheet Liability Exception Disk drive defects refers to defects that involve adjustment repair or replacement Fujitsu is not liable for any other disk drive defects such as those caused by user misoperation or mishandling inappropriate operating environments defects in the power supply or cable problems of the host system or ...

Page 8: ...This page is intentionally left blank ...

Page 9: ...orm the procedure correctly Task Alert message Page Normal Operation Data corruption Avoid mounting the disk near strong magnetic sources such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handlin...

Page 10: ...This page is intentionally left blank ...

Page 11: ... PRODUCT MANUAL C141 E224 This manual Device Overview Device Configuration Installation Conditions Theory of Device Operation Interface Operations MHV2120BH MHV2100BH MHV2080BH MHV2060BH MHV2040BH DISK DRIVES MAINTENANCE MANUAL C141 F074 Maintenance and Diagnosis Removal and Replacement Procedure ...

Page 12: ...This page is intentionally left blank ...

Page 13: ... Environmental Specifications 1 9 1 5 Acoustic Noise 1 10 1 6 Shock and Vibration 1 10 1 7 Reliability 1 11 1 8 Error Rate 1 12 1 9 Media Defects 1 12 1 10 Load Unload Function 1 12 1 10 1 Recommended power off sequence 1 13 1 11 Advanced Power Management APM 1 13 1 12 Interface Power Management IPM 1 15 1 12 1 Host initiated interface power management HIPM 1 15 1 12 2 Device initiated interface p...

Page 14: ...supply segment 3 10 3 3 3 Connector specifications for host system 3 10 3 3 4 SATA interface cable connection 3 11 3 3 5 Note about SATA interface cable connection 3 11 CHAPTER 4 Theory of Device Operation 4 1 4 1 Outline 4 2 4 2 Subassemblies 4 2 4 2 1 Disk 4 2 4 2 2 Spindle 4 2 4 2 3 Actuator 4 2 4 2 4 Air filter 4 3 4 3 Circuit Configuration 4 3 4 4 Power on Sequence 4 6 4 5 Self calibration 4 ...

Page 15: ... Signal interface regulation 5 4 5 1 2 1 Out of band signaling 5 4 5 1 2 2 Primitives descriptions 5 5 5 1 3 Electrical specifications 5 7 5 1 4 Connector pinouts 5 10 5 1 5 P11 function 5 11 5 1 5 1 Staggered Spin up 5 11 5 1 5 2 Driving Ready LED 5 11 5 1 6 Hot Plug 5 13 5 2 Logical Interface 5 14 5 2 1 Communication layers 5 15 5 2 2 Outline of the Shadow Block Register 5 16 5 2 3 Outline of th...

Page 16: ... S X 40 or X 41 5 40 6 SEEK X 70 to X 7F 5 42 7 EXECUTE DEVICE DIAGNOSTIC X 90 5 43 8 INITIALIZE DEVICE PARAMETERS X 91 5 44 9 DOWNLOAD MICROCODE X 92 5 45 10 STANDBY IMMEDIATE X 94 or X E0 5 47 11 IDLE IMMEDIATE X 95 or X E1 UNLOAD IMMEDIATE X 95 or X E1 5 48 12 STANDBY X 96 or X E2 5 50 13 IDLE X 97 or X E3 5 51 14 CHECK POWER MODE X 98 or X E5 5 53 15 SLEEP X 99 or X E6 5 54 16 SMART X B0 5 55 ...

Page 17: ... 41 READ LOG EXT X 2F 5 131 42 WRITE SECTOR S EXT X 34 5 135 43 WRITE DMA EXT X 35 5 136 44 SET MAX ADDRESS EXT X 37 5 137 45 WRITE MULTIPLE EXT X 39 5 139 46 WRITE LOG EXT X 3F 5 140 47 READ VERIFY SECTOR S EXT X 42 5 142 48 FLUSH CACHE EXT X EA 5 143 49 WRITE MULTIPLE FUA EXT X CE 5 144 50 WRITE DMA FUA EXT X 3D 5 145 51 READ FP DMA QUEUED X 60 5 146 52 WRITE FP DMA QUEUED X 61 5 147 5 3 3 Error...

Page 18: ...ower Save 6 8 6 2 1 Power save mode 6 8 6 2 2 Power commands 6 10 6 3 Power Save Controlled by Interface Power Management IPM 6 11 6 3 1 Power save mode of the interface 6 11 6 4 Read ahead Cache 6 13 6 4 1 Data buffer structure 6 13 6 4 2 Caching operation 6 14 6 4 3 Using the read segment buffer 6 16 6 4 3 1 Miss hit 6 16 6 4 3 2 Sequential hit 6 17 6 4 3 3 Full hit 6 17 6 4 3 4 Partial hit 6 19...

Page 19: ...ure 4 2 Circuit configuration 4 5 Figure 4 3 Power on operation sequence 4 6 Figure 4 4 Read write circuit block diagram 4 9 Figure 4 5 Frequency characteristic of programmable filter 4 10 Figure 4 6 Block diagram of servo control circuit 4 12 Figure 4 7 Physical sector servo configuration on disk surface 4 16 Figure 4 8 Servo frame format 4 17 Figure 5 1 Interface signals 5 2 Figure 5 2 Example o...

Page 20: ...5 17 DMA data out command protocol 5 156 Figure 5 18 READ FP DMA QUEUED command protocol 5 158 Figure 5 19 WRITE FP DMA QUEUED command protocol 5 159 Figure 5 20 Power on sequence 5 160 Figure 5 21 COMRESET sequence 5 161 Figure 6 1 Response to power on when the host is powered on earlier than the device 6 2 Figure 6 2 Response to power on when the device is powered on earlier than the host 6 3 Fi...

Page 21: ...de 5 43 Table 5 8 Operation of DOWNLOAD MICROCODE 5 45 Table 5 9 Example of rewriting procedure of data 512K Bytes 80000h Bytes of microcode 5 46 Table 5 10 Features Field values subcommands and functions 5 56 Table 5 11 Format of device attribute value data 5 60 Table 5 12 Format of guarantee failure threshold value data 5 60 Table 5 13 Off line data collection status 5 63 Table 5 14 Self test ex...

Page 22: ...ination of Identifier and Security level and operation of the lock function 5 110 Table 5 29 Contents of security password 5 118 Table 5 30 Data format of Read Log Ext log page 10h 5 133 Table 5 31 Tag field information 5 133 Table 5 32 Data format of Read Log Ext log page 11h 5 134 Table 5 33 Counter Identifier information 5 134 Table 5 34 Command code and parameters 5 148 ...

Page 23: ...1 10 Load Unload Function 1 11 Advanced Power Management APM 1 12 Interface Power Management IPM 1 13 Restriction of Use of Hazardous Substances Overview and features are described in this chapter and specifications and power requirement are described The disk drive is 2 5 inch hard disk drives with built in disk controllers These disk drives use the SATA interface protocol which has a high speed ...

Page 24: ...BH respectively 4 High speed Transfer rate The disk drive the MHV2xxxBH Series has an internal data rate up to 61 3 MB s The disk drive supports an external data rate 1 5Gbps 150MB s Serial ATA Generation 1 And the disk drive realizes a high performance by high speed transfer rate combined with Native Command Queuing NCQ 5 Average positioning time Use of a rotary voice coil motor in the head posit...

Page 25: ...cution of a disk read command the disk drive automatically reads the subsequent data block and writes it to the data buffer read ahead operation This cache system enables fast data access The next disk read command would normally cause another disk access But if the read ahead data corresponds to the data requested by the next read command the data in the buffer can be transferred instead 4 Error ...

Page 26: ...ad and seek Minimum Track Track Average Maximum Full 1 5 ms typ Read 12 ms typ 22 ms typ Start time 4 0 sec typ Interface Compliant with ATA ATAPI 7 SATA II Ext to SATA1 0a SATA II Electrical Spec 1 0 Data Transfer Rate 2 To From Media To From Host 61 3MB s Max 1 5 Gbps 150 MB s Data Buffer Size 3 8 MB 8 388 608 bytes Physical Dimensions Height Width Depth 9 5 mm 100 0 mm 70 0 mm 4 Weight 101 g ma...

Page 27: ... 2 lists the model names and product numbers of the disk drive The model name does not necessarily correspond to the product number as listed in Table 1 2 since some models have been customized and have specifications that are different from those for the standard model If a disk drive is ordered as a replacement drive the product number must be the same as that of the drive being replaced Table 1...

Page 28: ...Slope of an input voltage at rise The following figure shows the restriction of the slope which is 5 V input voltage at rise The permissible range of 5 V slope is from 1V 20 µsec to 1V 20 msec under the voltage range is between 2 0V and 4 5V V T The slope limitation refers only to this range Input Voltage V Time sec 0V 2 0V 4 5V Slope S V T V sec S 1V 20us to 1V 20ms Figure 1 1 Permissible range o...

Page 29: ...ltage like the bottom figure isn t to occur at 5 V when power is turned off and a thing with no ringing Permissible level 0 2 V Voltage V 5 0 100 200 300 400 500 600 700 800 Time ms 4 3 2 1 0 1 Figure 1 2 Negative voltage at 5 V when power is turned off ...

Page 30: ...k E MHV2100BH 0 0075 W GB rank E MHV2080BH 0 0100 W GB rank E MHV2060BH 0 0150 W GB rank D MHV2040BH 1 Maximum current and power at starting spindle motor 2 Current and power level when the operation command that accompanies a transfer of 63 sectors is executed 3 times in 100 ms 3 Power requirements reflect typical values for 5 V power 4 Energy efficiency based on the Law concerning the Rational U...

Page 31: ...nate the need to be concerned with the power on off sequence 1 4 Environmental Specifications Table 1 4 lists the environmental specifications Table 1 4 Environmental specifications Item Specification Temperature Operating Non operating Thermal Gradient 5 C to 55 C ambient 5 C to 60 C disk enclosure surface 40 C to 65 C 20 C h or less Humidity Operating Non operating Maximum Wet Bulb 8 to 90 RH No...

Page 32: ... 1 6 lists the shock and vibration specification Table 1 6 Shock and vibration specification Item Specification Vibration Swept sine 1 4 octave per minute Operating Non operating 5 to 500 Hz 9 8m s 2 0 peak 1G 0 peak without non recovered errors 5 to 500 Hz 49m s 2 0 peak 5G 0 peak no damage Shock half sine pulse Operating Non operating 2940 m s 2 0 peak 300G 0 peak 2ms duration without non recove...

Page 33: ...repair MTTR is 30 minutes or less if repaired by a specialist maintenance staff member 3 Service life In situations where management and handling are correct the disk drive requires no overhaul for five years when the DE surface temperature is less than 48 C When the DE surface temperature exceeds 48 C the disk drives requires no overhaul for five years or 20 000 hours of operation whichever occur...

Page 34: ...7 seek operations 1 9 Media Defects Defective sectors are replaced with alternates when the disk drive is formatted prior to shipment from the factory low level format Thus the hosts see a defect free device Alternate sectors are automatically accessed by the disk drive The user need not be concerned with access to alternate sectors 1 10 Load Unload Function The Load Unload function is a mechanism...

Page 35: ...execution 2 Head Unload Standby Immediate command execution 3 Wait Status Checking whether bit 7 of the status register was set to 0 wait to complete STANDBY IMMEDIATE command 4 HDD power supply cutting 1 11 Advanced Power Management APM The disk drive automatically shifts to the power saving mode according to the setting of the APM mode under the idle condition The APM mode can be chosen with a S...

Page 36: ...s been exceeded Mode 0 Mode shifts from Active condition to Active Idle in 0 2 1 2 and to Low Power Idle in 15 minutes Mode 1 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds Mode 2 Mode shifts from Active condition to Active Idle in 0 1 0 2 seconds and to Low Power Idle in 10 0 27 5 seconds After 10 0 40 0 seconds in Low Power Idle the...

Page 37: ...o two kinds of IPM modes automatically under the Idle condition 1 Partial mode PMREQ_P is sent when the disk drive requests the Partial mode 2 Slumber mode PMREQ_S is sent when the disk drive requests the Slumber mode I F power states 1 Active state The SATA interface is active and data can be sent and received 2 Partial state The SATA interface is in the Power Down state In this state the interfa...

Page 38: ...ut the exemption of RoHS Directive see note 1 RoHS Directive Directive 2002 95 EC of the European parliament and of the council on the Restriction of the use of certain Hazardous Substances in electrical and electronic equipment Notes 1 There are some exemption in RoHS directive for example Lead in glass of electronic components 2 Some particulars under consideration have not determined at present...

Page 39: ... CHAPTER 2 Device Configuration 2 1 Device Configuration 2 2 System Configuration This chapter describes the internal configurations of the hard disk drives and the configuration of the systems in which they operate ...

Page 40: ...t drive Sensor less DC motor 4 Actuator The actuator uses a revolving voice coil motor VCM structure which consumes low power and generates very little heat The head assembly at the edge of the actuator arm is controlled and positioned by feedback of the servo information read by the read write head If the power is not on or if the spindle motor is stopped the head assembly stays on the ramp out o...

Page 41: ...Serial ATA interface and it realized a high performance by integration into LSI 2 2 System Configuration 2 2 1 SATA interface Figure 2 2 shows the SATA interface system configuration The disk drive complies with ATA ATAPI 7 SATA II Extensions to Serial ATA 1 0a and SATA II Electrical Spec 1 0 2 2 2 Drive connection Serial ATA Adapter Driver Operating System Application 1 Application 2 Application ...

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Page 43: ...ion Conditions 3 1 Dimensions 3 2 Mounting 3 3 Connections with Host System This chapter gives the external dimensions installation conditions surface temperature conditions cable connections and switch settings of the hard disk drives ...

Page 44: ...nnectors are not included in these dimensions 2 Dimension from the center of the user tap to the base of the connector pins 3 Length of the connector pins 4 Dimension from the outer edge of the user tap to the center of the connector pins 5 Dimension from the outer edge of the user tap to the innermost edge of the connector pins Figure 3 1 Dimensions ...

Page 45: ...ee the FUJITSU 2 5 INCH HDD INTEGRATION GUIDANCE C141 E144 1 Orientation Figure 3 2 illustrates the allowable orientations for the disk drive a Horizontal 1 b Horizontal 2 c Vertical 1 d Vertical 2 e Vertical 3 f Vertical 4 Figure 3 2 Orientation gravity gravity gravity ...

Page 46: ...49N m 5kgf cm m 5kgf cm When attaching the HDD to the system frame do not allow the system frame to touch parts cover and base other than parts to which the HDD is attached 3 Limitation of mounting Note These dimensions are recommended values if it is not possible to satisfy them contact us Screw Screw Details of A 3 0 or less 3 0 or less Frame of system cabinet Frame of system cabinet B PCA A 2 2...

Page 47: ...use of breather hole mounted to the HDD do not allow this to close during mounting Locating of breather hole is shown as Figure 3 4 For breather hole of Figure 3 4 at least do not allow its around φ 2 4 to block Figure 3 4 Location of breather ...

Page 48: ...erature from exceeding 60 C Provide air circulation in the cabinet such that the PCA side in particular receives sufficient cooling To check the cooling efficiency measure the surface cover temperatures of the DE Regardless of the ambient temperature this surface cover temperature must meet the standards listed in Table 3 1 Figure 3 5 shows the temperature measurement point 1 Figure 3 5 Surface co...

Page 49: ...es such as loud speakers Ensure that the disk drive is not affected by external magnetic fields Damage Do not press the cover of the disk drive Pressing it too hard the cover and the spindle motor contact which may cause damage to the disk drive Static When handling the device disconnect the body ground 500 kΩ or greater Do not touch the printed circuit board but hold it by the edges 6 Handling ca...

Page 50: ...ue of the screw strictly M3 0 49N m 5 kgf cm Recommended equipments Contents Model Maker Wrist strap JX 1200 3056 8 SUMITOMO 3M ESD ESD mat SKY 8A Color Seiden Mat Achilles Shock Low shock driver SS 6500 HIOS Place the shock absorbing mat on the operation table and place ESD mat on it Use the Wrist strap Do not hit HDD each other Do not stack when carrying Do not place HDD vertically to avoid fall...

Page 51: ...th Host System 3 3 1 Device connector The disk drive has the SATA interface connectors listed below for connecting external devices Figure 3 8 shows the locations of these connectors and terminals SATA interface and power connectors PCA Figure 3 8 Connector locations ...

Page 52: ...n the signal segment View from the connector side View from the PCA side Signal segment Figure 3 9 Power supply pins CN1 3 3 3 Connector specifications for host system Table 3 2 lists the recommended specifications for the host interface connectors Table 3 2 The recommended connector specifications for the host system Segment Name Model Manufacturer SATA interface and power supply Host receptacle ...

Page 53: ...ce cable connection Take note of the following precaution about plugging a SATA interface cable into the SATA interface connector of the disk drive and plugging the connector into a host receptacle When plugging together the disk drive SATA interface connector and the host receptacle or SATA interface cable connector do not apply more than 10 kgf of force in the connection direction once they are ...

Page 54: ...This page is intentionally left blank ...

Page 55: ... Circuit Configuration 4 4 Power on Sequence 4 5 Self calibration 4 6 Read write Circuit 4 7 Servo Control This chapter explains basic design concepts of the disk drive Also this chapter explains subassemblies of the disk drive each sequence servo control and electrical circuit blocks ...

Page 56: ...s disks with an outer diameter of 65 mm and an inner diameter of 20 mm Servo data is recorded on each cylinder total 134 Servo data written at factory is read out by the read head For servo data see Section 4 7 4 2 2 Spindle The spindle consists of a disk stack assembly and spindle motor The disk stack assembly is activated by the direct drive sensor less DC spindle motor which has a speed of 5 40...

Page 57: ...egrated into LSI with MCU and HDC The PreAMP consists of the write current switch circuit that flows the write current to the head coil and the voltage amplifier circuit that amplitudes the read output from the head The RDC is the read demodulation circuit using the Modified Extended Partial Response MEEPR and contains the Viterbi detector programmable filter adaptable transversal filter times bas...

Page 58: ...nterface control and data transfer control Data buffer management Sector format control Defect management ECC control Error recovery and self diagnosis FROM Combo 1 2V 3 3V 3 3V 5 0V 3 0V MCU HDC RDC Serial PreAMP 3 3V 1 2V S DRAM SVC generator circuit generator circuit Figure 4 1 Power supply configuration ...

Page 59: ...uration C141 E224 4 5 MCU HDC RDC HDC MCU RDC Data Buffer SDRAM Serial Flash ROM SVC Crystal 40MHz R W Pre Amp Thermistor VCM HEAD SP Motor Media DE PCA Serial ATA Interface Shock Sensor Figure 4 2 Circuit configuration ...

Page 60: ...rated speed the head assembly is loaded on the disk d The disk drive positions the heads onto the SA area and reads out the system information e The drive becomes ready The host can issue commands f The disk drive executes self calibration This collects data for VCM torque and mechanical external forces applied to the actuator and updates the calibrating value Figure 4 3 Power on operation sequenc...

Page 61: ...ory calibration The measured values are stored in the SA cylinder In the self calibration the compensating value is updated using the value in the SA cylinder 2 Compensating open loop gain Torque constant value of the VCM has dispersion for each drive and varies depending on the cylinder that the head is positioned To realize the high speed seek operation the value that compensates torque constant...

Page 62: ...ocessing during self calibration This enables the host to execute the command without waiting for a long time even when the disk drive is performing self calibration The command execution wait time is about maximum 72 ms When the error rate of data reading writing or seeking becomes lower than the specified value self calibration is performed to maintain disk drive stability If the disk drive rece...

Page 63: ...nd the current in writing Each channel is connected to each data head and PreAMP switches channel by serial I O In the event of any abnormalities including a head short circuit or head open circuit the write unsafe signal is generated so that abnormal write does not occur 4 6 2 Write circuit The write data is transferred from the hard disk controller HDC to the RDC in LSI The write data is sent to...

Page 64: ...uctuates The AGC amplifier output is maintained at a constant level even when the head output fluctuates due to the head characteristics or outer inner head positions 2 Programmable filter circuit The programmable filter circuit has a low pass filter function that eliminates unnecessary high frequency noise component and a high frequency boost up function that equalizes the waveform of the read si...

Page 65: ...cuit demodulates data according to the survivor path sequence 4 6 4 Digital PLL circuit The drive uses constant density recording to increase total capacity This is different from the conventional method of recording data with a fixed data transfer rate at all data area In the constant density recording method data area is divided into zones by radius and the data transfer rate is set so that the ...

Page 66: ...ator motor is controlled according to the servo data that is written on the data side beforehand 4 7 1 Servo control circuit Figure 4 6 is the block diagram of the servo control circuit The following describes the functions of the blocks Figure 4 6 Block diagram of servo control circuit Head Spindle motor CSR VCM Position Sense VCM current CSR Current Sense Resister VCM Voice Coil Motor 1 MPU HDC ...

Page 67: ... indicate the head position from the servo data on the data surface From the servo area on the data area surface via the data head the burst signals of EVEN1 ODD EVEN2 are output as shown in Figure 4 8 in subsequent to the servo mark gray code that indicates the cylinder position and index information The servo signals do A D convert by Fourier demodulator in the servo burst capture circuit At tha...

Page 68: ...t is a power amplitude circuit that receives signals from the spindle motor control circuit and feeds currents to the spindle motor 7 VCM current sense resistor CSR This resistor controls current at the power amplifier by converting the VCM current into voltage and feeding back ...

Page 69: ...w 1 Inner guard band This area is located inside the user area and the rotational speed of the VCM can be controlled on this cylinder area for head moving 2 Data area This area is used as the user data area and SA area 3 Outer guard band This area is located at outer position of the user data area and the rotational speed of the spindle can be controlled on this cylinder area for head moving ...

Page 70: ...C erase area CYLn 1 CYLn CYLn 1 n even number W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code W R Recovery Servo Mark Gray Code EVEN1 ODD EVEN2 Post code MHV2120BH only PAD Diameter direction Figure 4 7 Physical sector servo configuration on disk surface ...

Page 71: ...rmat 1 Write read recovery This area is used to absorb the write read transient and to stabilize the AGC 2 Servo mark This area generates a timing for demodulating the gray code and position demodulating the burst signal by detecting the servo mark 3 Gray code including sector address bits This area is used as cylinder address The data in this area is converted into the binary data by the gray cod...

Page 72: ...t speed d If the head is stopped at the reference cylinder from there Track following control starts 2 Seek operation Upon a data read write request from the host the MPU confirms the necessity of access to the disk If a read write instruction is issued the MPU seeks the desired track The MPU feeds the VCM current via the D A converter and power amplifier to move the head The MPU calculates the di...

Page 73: ...r that repeating this order d During phase switching the spindle motor starts rotating in low speed and generates a counter electromotive force The SVC detects this counter electromotive force and reports to the MPU using a PHASE signal for speed detection e The MPU is waiting for a PHASE signal When no phase signal is sent for a specific period the MPU resets the SVC and starts from the beginning...

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Page 75: ...CHAPTER 5 Interface 5 1 Physical Interface 5 2 Logical Interface 5 3 Host Commands 5 4 Command Protocol 5 5 Power on and COMRESET This chapter gives details about the interface and the interface commands and timings ...

Page 76: ...end Device analog front end GND Figure 5 1 Interface signals An explanation of each signal is provided below TX TX These signals are the outbound high speed differential signals that are connected to the serial ATA cable RX RX These signals are the inbound high speed differential signals that are connected to the serial ATA cable TxData Serially encoded 10b data attached to the high speed serial d...

Page 77: ...dicates the COMWAKE out of band signal is being detected COMRESET COMINIT Host Signal from the out of band detector that indicates the COMINIT out of band signal is being detected Device Signal from the out of band detector that indicates the COMRESET out of band signal is being detected 5VDC GND 5VDC 5 V power supply to the disk drive GND Ground for each signal and 5 V power supply ...

Page 78: ...band signaling During OOB signaling transmissions the differential and common mode levels of the signal lines shall comply with the same electrical specifications as for in band data transmission specified as follows COMRESET COMINIT 106 7 ns 320 ns COMWAKE 106 7 ns 106 7 ns ...

Page 79: ...a frame when the transmitter does not have the next payload data ready for transmission HOLD is also transmitted on the backchannel when a receiver is not ready to receive additional payload data HOLDA Hold acknowledge This primitive is sent by a transmitter as long the HOLD primitive is received by its companion receiver PMNAK Power management denial Sent in response to a PMREQ_S or PMREQ_P when ...

Page 80: ...ver ready Current node host or device is ready to receive payload SOF Start of frame Start of a frame Payload and CRC follow to EOF SYNC Synchronization Synchronizing primitive always idle WTRM Wait for frame termination After transmission of any of the EOF the transmitter will transmit WTRM while waiting for reception status from receiver X_RDY Transmission data ready Current node host or device ...

Page 81: ...nterval ps 666 6667 666 4333 670 2333 ftol TX Frequency Long Term Stability ppm 350 350 fSSC Spread Spectrum Modulation Frequency kHz 30 33 SSCtol Spread Spectrum Modulation Deviation ppm 5000 0 Vcm dc DC Coupled Common Mode Voltage mV 250 200 450 Vcm ac coupled AC Coupled Common Mode Voltage mV 0 2000 Zdiff Nominal Differential Impedance ohm 100 Cac coupling AC Coupling Capacitance nF 12 tsettle ...

Page 82: ...Comments VdiffTX TX Differential Output Voltage mVppd 500 400 600 Differential nominal measured at Serial ATA connector on transmit side 250mV differential seria l ATA connector t20 80TX TX Rise Fall Time ps UI 0 15 20 80 0 41 20 80 Rise 20 80 at transmitter Fall 80 20 at transmitter tskewTX TX Differential Skew ps 20 TJ at Connector Data Data 5UI UI 0 355 DJ at Connector Data Data 5UI UI 0 175 TJ...

Page 83: ...n Max Comments Vthresh OOB Signal Detection Threshold mVppd 100 50 200 UIOOB UI During OOB Signaling ps 666 67 646 67 686 67 COMINIT COMRESET and COMWAKE Transmit Burst Length UIOOB 160 COMINIT COMRESET Transmit Gap Length UIOOB 480 COMWAKE Transmit Gap Length UIOOB 160 Units May detect Shall detect Shall not detect Comments COMWAKE Gap Detection Windows ns 55 T 175 101 3 T 112 T 55 or 175 COMINIT...

Page 84: ... 5 V power pre charge 2nd mate P8 V5 5 V power P9 V5 5 V power P10 Gnd 2nd mate P11 Staggered Spin up Mode Ready LED Staggered Spin up mode detect for input Ready LED drive for output For the specification of P11 see Section 5 1 5 in next page When the host system does not use these function the corresponding pin to be mated with P11 in the power cable receptacle connector shall be grounded P12 Gn...

Page 85: ...ctor a P11 Grounded 0 8 V or less Staggered Mode Disable The disk drive spins up at power on b P11 High level The P11 line in the host system is pulled up by resistor recommended value 1 to 5 1 kΩ to power supply in the host system Recommended voltage 2V 3 3V or less Staggered Mode Enable The drive does not spin up until after successful Phy initialization at power on 5 1 5 2 Driving Ready LED It ...

Page 86: ...Interface 5 12 C141 E224 Figure 5 2 Example of the circuit for driving Ready LED ...

Page 87: ...cation The equivalent circuit of 5V power supply at Hot Plugging is in the following figure It is necessary to choose pre charge resistor RL value which is in permissible range of 5V power supply specification at the host system Refer to the equivalent circuit when the optimized value of pre charge resistor RL It is recommended to choose the minimum value which is in permissible range of 5V power ...

Page 88: ...the host or device and between layers at the same level that link the host and device Figure 5 3 is a conceptual diagram of the communication layers Host Software control Buffer Memory DMA engine s Host located layers Physical Layer Link Layer Transport Layer Device located layers Physical Layer Link Layer Transport Layer Device Software control Buffer memory DMA engine s Application layer 4 Trans...

Page 89: ...al transfer requests between the host system and device Encodes serial data as 10 or 8 bit data then converts it into DWORD data Inserts auxiliary signals SOF CRC and EOF deletes auxiliary signals and communicates with the transport and physical layers Transport layer Exchanges data in communication with the link layer and builds the frame information structure FIS Contains a Shadow Block Register...

Page 90: ...Count Sector Count exp Sector Count Sector Number exp Sector Number Sector Number exp Sector Number Cylinder Low exp Cylinder Low Cylinder Low exp Cylinder Low Cylinder High exp Cylinder High Cylinder High exp Cylinder High Device Head Status Command Control Block registers Alternate Status Device Control Note Each of the Sector Count Sector Number Cylinder Low and Cylinder High fields has a highe...

Page 91: ...Device to Host or Host to Device Bidirectional DMA Setup Set Device Bits Device to Host SetDB BIST Active Bidirectional BIST Active PIO Setup Device to Host PIO Setup Data Host to Device or Device to Host Bidirectional DATA 5 2 3 2 Register Host to Device The Register Host to Device FIS has the following layout 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0...

Page 92: ...LBA Mid LBA Low 1 Reserved 0 LBA High exp LBA Mid exp LBA Low exp 0 2 Reserved 0 Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Reserved 0 Reserved 0 Reserved 0 4 Figure 5 5 Register Device to Host FIS layout The Register Device to Host FIS is used when information concerning the Shadow Register Block in the host adapter is updated This FIS indicates that the device has completed a command ...

Page 93: ... 41h 0 0 TAG 1 0 2 Reserved 0 3 DMA Buffer Offset 4 DMA Transfer Count 5 Reserved 0 6 Figure 5 7 DMA Setup Device to Host or Host to Device FIS layout The DMA Setup Device to Host or Host to Device FIS communicates the start of a first party DMA access to the host system This FIS is used to request the host system or device to set up the DMA controller before the start of a DMA data transfer A Aut...

Page 94: ...ack mode This FIS can be sent by either the host system or device The following combinations of pattern definitions are supported Table 5 5 BIST combinations T A S L F P V SC Reg Contents 1 1 09h SATA Phy Analog Loopback Mode 1 10h Far End Retimed Loopback Mode 1 1 C0h No ALIGN Transmit_only Mode Scramble ON 1 1 1 1 E0h No ALIGN Transmit_only Mode Scramble OFF 1 1 1 C4h No ALIGN Transmit_only with...

Page 95: ...Reserved 0 FIS Type 5Fh 0 Dev Head Cyl High Cyl Low Sector Number 1 Reserved 0 Cyl High exp Cyl Low exp Sector Num exp 0 2 E_Status Reserved 0 Sector Count exp Sector Count 3 Reserved 0 Transfer Count 4 Figure 5 10 PIO Setup Device to Host FIS layout The PIO Setup FIS is a device to host FIS FIS Type 5Fh The PIO Setup FIS is used by the device to provide the host adapter with the data transfer cou...

Page 96: ...adow Register Block E_Status Contains the new value of the status register of the task file block for correct synchronization of data transfers to host Error Contains the new value of the Error register of the Command Block at the conclusion of all subsequent Data to Device frames I Interrupt bit This bit reflects the interrupt bit line of the device R Reserved 0 Sector Count Holds the contents of...

Page 97: ...pending state if both the BSY bit and the DRQ bit in the shadow Status register are zero when the frame is received Error Contains the new value of the Error register of the Shadow Register Block Status Hi Contains the new value of bits 6 5 and 4 of the Status register of the Shadow Register Block Status Lo Contains the new value of bits 2 1 and 0 of the Status register of the Shadow Register Bloc...

Page 98: ...rite process Bit 5 Unused Bit 4 ID Not Found IDNF This bit indicates an error except for bad sector uncorrectable error and SB not found Or SATA Frame Error Write SFRW This bit indicates that a SATA communication error has been encountered during the write process In this case bit4 and bit2 are set both Bit 3 SATA Frame Error Read SF RR This bit indicates that a SATA communication error has been e...

Page 99: ...he host system That is this field indicates the number of remaining sectors that the data has not been transferred due to the error However as of the last sector of PIO transfer SC 1 indicates the normal completion The contents of this field also have other definitions Refer to 5 4 4 Sector Number Field exp The contents of this field indicates the starting sector number for the subsequent command ...

Page 100: ...The contents of this field indicate the device and the head number When executing INITIALIZE DEVICE PARAMETERS command the contents of this field defines the number of heads minus 1 a maximum head No Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 X L X X HS3 HS2 HS1 HS0 Bit 7 Unused Bit 6 L 0 for CHS mode and 1 for LBA mode Bit 5 Unused Bit 4 Unused Bit 3 HS3 CHS mode head address 3 2 3 bit 27 fo...

Page 101: ...set Bit 6 Device Ready DRDY bit This bit indicates that the device is capable to respond to a command The IDD checks its status when it receives a command If an error is detected not ready state the IDD clears this bit to 0 This is cleared to 0 at power on and it is cleared until the rotational speed of the spindle motor reaches the steady speed Bit 5 Device Write Fault DF bit This bit indicates t...

Page 102: ...evice is not required to execute the DASP handshake 11 E_Status Field This field is in the PIO Setup FIS The field contents are the same as those described in 8 Status Field However the values in the Status field are those before a PIO data transfer and the values in the E_Status field are those when a PIO data transfer is completed 12 DMA Buffer Offset Field This field is in the DMA Setup FIS rep...

Page 103: ... code and parameters Table 5 6 lists the supported commands command code and the related fields to be written necessary parameters at command execution Table 5 6 Command code and parameters 1 3 COMMAND CODE Bit PARAMETER USED COMMAND NAME 7 6 5 4 3 2 1 0 FR SC SN CY DH RECALIBRATE 0 0 0 1 X X X X N N N N D READ SECTOR S 0 0 1 0 0 0 0 R N Y Y Y Y WRITE SECTOR S 0 0 1 1 0 0 0 R N Y Y Y Y WRITE VERIF...

Page 104: ...FER 1 1 1 0 0 1 0 0 N N N N D FLUSH CACHE 1 1 1 0 0 1 1 1 N N N N D WRITE BUFFER 1 1 1 0 1 0 0 0 N N N N D IDENTIFY DEVICE 1 1 1 0 1 1 0 0 N N N N D IDENTIFY DEVICE DMA 1 1 1 0 1 1 1 0 N N N N D SET FEATURES 1 1 1 0 1 1 1 1 Y N N N D SECURITY SET PASSWORD 1 1 1 1 0 0 0 1 N N N N D SECURITY UNLOCK 1 1 1 1 0 0 1 0 N N N N D SECURITY ERASE PREPARE 1 1 1 1 0 0 1 1 N N N N D SECURITY ERASE UNIT 1 1 1 1...

Page 105: ... 0 1 0 N Y Y Y D FLUSH CACHE EXT 1 1 1 0 1 0 1 0 N N N N D WRITE MULTIPLE FUA EXT 1 1 0 0 1 1 1 0 N Y Y Y D WRITE DMA FUA EXT 0 0 1 1 1 1 0 1 N Y Y Y D READ FP DMA QUEUED 0 1 1 0 0 0 0 0 Y Y Y Y D WRITE FP DMA QUEUED 0 1 1 0 0 0 0 1 Y Y Y Y D CY cylinder field DH device head field FR features field SC sector count field SN sector number field R Retry at error 1 Without retry 0 With retry Y Necessa...

Page 106: ...ress LSB LBA 15 8 SN EXP LBA 31 24 SN EXP LBA 31 24 SN Start sector No LBA 7 0 SN End sector No LBA 7 0 SC EXP Transfer sector count 15 8 SC EXP X 00 SC Transfer sector count 7 0 SC X 00 FR EXP xx FR xx ER Error information CH EXP Cylinder High Field EXP CL EXP Cylinder Low Field EXP CM Command Field DH Device Head Field ER Error Field FR EXP Features Field EXP L LBA Logical Block Address setting ...

Page 107: ...r reporting conditions 1 An error was detected during head positioning ST 51h ER 02h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 0 1 x x x x DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error inform...

Page 108: ...block registers contain the cylinder head and sector addresses in the CHS mode or logical block address in the LBA mode of the last sector read If an unrecoverable disk read error occurs in a sector the read operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head and the sector addresses of the sector in the CHS mode or the logical block ...

Page 109: ...LSB LBA Start sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 01 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred ...

Page 110: ... sector addresses of the last sector written If an disk error occurs during multiple sector write operation the write operation is terminated at the sector where the error occurred Shadow block registers contain the cylinder the head the sector addresses in the CHS mode or the logical block address in the LBA mode of the sector where the error occurred Error reporting conditions 1 A specified addr...

Page 111: ...tart sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this fiel...

Page 112: ...tion after a transfer of dummy data ST 51h ER 10h 3 A write fault was detected when the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if the status indicating a completed transfer STS 50h is returned and a data write operation failed because a write fault was detected during the data write operation Abort will be returned for all subsequent ATA commands ST 71h ER 04h Th...

Page 113: ...atus information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated because of an error the number of remaining sectors for which data has not been written or verified is set in this register ...

Page 114: ...k address in the LBA mode of the sector where the error occurred The Sector Count field indicates the number of sectors that have not been verified Error reporting conditions 1 A specified address exceeds the range where read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable dis...

Page 115: ...ead ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this register ...

Page 116: ...ress exceeds the range where the head can be positioned ST 51h ER 10h 2 Head positioning is not possible because an error occurred ST 51h ER 10h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 1 1 1 x x x x DH x L x x HD No LBA CH CL SN SC FR Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB xx xx At com...

Page 117: ...pleted No error detected HDC diagnostic error Data buffer diagnostic error Memory diagnostic error Reading the system area is abnormal Calibration abnormal Note The device responds to this command with the result of power on diagnostic test Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 0 0 1 0 0 0 0 D...

Page 118: ...d are retained even after soft reset and COMRESET issuance or power save operation regardless of the setting of disabling the reverting to default setting The operation is always performed in CHS mode with the command ignoring any setting of LBA mode Error reporting conditions 1 00h is specified in the SC field ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance S...

Page 119: ... microcode rewriting according to Subcommand code Rewriting is also possible simultaneously with the data transfer Refer to Table 5 8 In the data transfer of Subcommand code 01h transfer by which data is divided into multiple times is possible Refer to Table 5 9 After the designation of rewriting by Subcommand code 07h reactivates in the device for the update of the rewriting microcode of the micr...

Page 120: ...000h FR 07h Transfer of 512 KB Firmware rewriting execution Transfer example 3 1 CMD 92h SN SC 0400h FR 07h Transfer of 512 KB and Firmware rewriting execution Transfer example 4 1 CMD 92h SN SC 0100h FR 0lh 2 CMD 92h SN SC 0100h FR 0lh 3 CMD 92h SN SC 0100h FR 0lh 4 CMD 92h SN SC 0100h FR 07h Transfer of 128 KB 0 to 127 KB from the beginning Transfer from 128 to 255 KB Transfer from 256 to 383 KB...

Page 121: ...command does not support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 94 or X E0 DH x x x x Xx CH CL SN SC FR xx xx xx xx Xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Xx CH CL SN SC ER xx xx xx xx Error information ...

Page 122: ...ost system This command does not support the APS timer function Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 95 or X E1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error inf...

Page 123: ...ects the normal not emergency load unload guarantee count per the device life Even if the device executes reading look ahead operation or executes writing operation the device unloads the head s to the ramp position as soon as possible when received the IDLE IMMEDIATE command with the Unload Feature When the writing operation is stopped the device keeps the unwritten data And the device keeps the ...

Page 124: ...tomatically enters Standby mode If the Sector Count field value is 0 the APS timer is disabled when the command is received Under the standby mode the spindle motor is stopped Thus when the command involving a seek such as READ SECTOR s command is received the device processes the command after driving the spindle motor Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h...

Page 125: ...ice enters standby mode The APS timer is set to prohibition if the Sector Count field s value was 0 when device has received this command The period of timer count is set depending on the value of the Sector Count register as shown below Sector Count field value Point of timer 0 X 00 Timeout disabled 1 to 240 X 01 to X F0 Value 5 seconds 241 to 251 X F1 to X FB Value 240 30 min 252 X FC 21 minutes...

Page 126: ...Interface 5 52 C141 E224 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 127: ...he device reports the status to the host system Power save mode Sector Count field During moving to Standby mode Standby mode X 00 Idle mode X FF Active mode X FF Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 98 or X E5 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Reg...

Page 128: ...he sleep mode In the sleep mode the spindle motor is stopped The only way to release the device from sleep mode is to execute a software or COMRESET Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM X 99 or X E6 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers content...

Page 129: ...ld 4Fh in the Cylinder Low field and C2h in the Cylinder High field If the key values are incorrect the Aborted Command error is issued If the failure prediction function is disabled the device returns the Aborted Command error to subcommands other than those of the SMART Enable Operations with the Features field set to D8h If the failure prediction function is enabled the device collects and upda...

Page 130: ...e that attributes were saved then the attributes are saved However if the automatic attribute save function is disabled the attributes are not saved Upon receiving this subcommand a device enables or disables the automatic attribute save function and transfers the RegDH then reports the status In this drive this function is enabled at the shipment from the factory X D3 SMART SAVE ATTRIBUTE VALUES ...

Page 131: ...the SMART selective self test log data format X D6 SMART WRITE LOG A device which receives this sub command when it has prepared to receive data from the host computer it transfers the PIOSU Next it receives data from the host computer and writes the specified log sector in the Sector Number Field SN SC Log sector 09h 01h SMART selective self test log 80h 9Fh 01h 10h Host vendor log The host can w...

Page 132: ...ve s power is switched on or off If 24 hours have passed since the power was switched on or since the last time that off line data were collected off line data collection is performed without relation to any command from the host computer The host must regularly issue the SMART READ DATA subcommand Features field D0h SMART SAVE ATTRIBUTE VALUES subcommand Features field D3h or SMART RETURN STATUS ...

Page 133: ...e prediction status C2h 2Ch Key failure prediction status 4Fh F4h xx xx Error information The attribute value information is 512 byte data the format of this data is shown the following Table 5 11 The host can access this data using the SMART READ DATE subcommand Features field D0h The guarantee failure threshold value data is 512 byte data the format of this data is shown the following Table 5 12...

Page 134: ...16F Off line data collection capability 170 171 Trouble prediction capability flag 172 Error logging capability 173 Self test error detection point 174 Simple self test Quick Test execution time min 175 Comprehensive self test Comprehensive Test execution time min 176 Conveyance self test execution time min 177 to 181 Reserved 182 to 1FE Vendor unique 1FF Check sum Table 5 12 Format of guarantee f...

Page 135: ...ibute name 0 Indicates unused attribute data 1 Read Error Rate 2 Throughput Performance 3 Spin Up Time 4 Start Stop Count 5 Reallocated Sector Count 7 Seek Error Rate 8 Seek Time Performance 9 Power On Hours Count 10 Spin Retry Count 12 Drive Power Cycle Count 192 Emergency Retract Cycle Count 193 Load Unload Cycle Count 194 HDA Temperature 195 ECC On the Fly Count 196 Reallocated Event Count 197 ...

Page 136: ...ed even if SMART is disabled 6 to 15 Reserve bit Current attribute value It indicates the normalized value of the original attribute value The value deviates in a range of 01h to 64h range of 01h to C8h for the Ultra ATA CRC error rate and communication error rate It indicates that the closer the value is to 01h the higher the possibility of a failure The host compares the attribute value with the...

Page 137: ... execution status Table 5 14 Self test execution status Bit Meaning 0 to 3 Remainder of the self test is indicated as a percentage in a range of 0h to 9h corresponding to 0 to 90 4 to 7 Self test execution status 0h Self test has ended successfully or self test has not been executed 1h Self test is suspended by the host 2h Self test is interrupted by a soft reset COMRESET from the host 3h Self tes...

Page 138: ...ing Technology is supported 4 If this bit is 1 it indicates that the SMART Self test function is supported 5 If this bit is 1 it indicates that the SMART Conveyance Self test is supported 6 If this bit is 1 it indicates that the SMART Selective Self test is supported 7 Reserved bits Failure prediction capability flag Table 5 16 Failure prediction capability flag Bit Meaning 0 If this bit is 1 it i...

Page 139: ...ved 100 Number of sector 101 Address 80h Reserved 102 to 13F Address 81h to Address 9Fh 102 and 13F are both the same format as 100 101 140 to 1FF Reserved SMART error logging If the device detects an unrecoverable error during execution of a command received from the host the device registers the error information in the SMART Summary Error Log see Table 5 19 and the SMART Comprehensive Error Log...

Page 140: ...33 Features field value 34 Sector Count field value 35 Sector Number field value 36 Cylinder Low field value 37 Cylinder High field value 38 Drive Head field value 39 Command field value 3A to 3D Command data structure Elapsed time after the power on sequence unit ms 3E Reserved 3F Error field value 40 Sector Count field value 41 Sector Number field value 42 Cylinder Low field value 43 Cylinder Hi...

Page 141: ...dicates the status register when an error occurs Total number of drive errors Indicates total number of errors registered in the error log Checksum Two s complement of the lower byte obtained by adding 511 byte data one byte at a time from the beginning Status Bits 0 to 3 Indicates the drive status when received error commands according to the following table Bits 4 to 7 Vendor unique Status Meani...

Page 142: ...ructure 5n 4 16A 1C3 5 th Error Log Data Structure5 Error Log Data Structure 5n 5 1C4 1C5 Total number of drive errors Reserved 1C6 1FE Reserved Reserved 1FF Check sum Check sum n indicates sector number in the Error Log The first sector is 0 SMART Self Test The host computer can issue the SMART Execute Off line Immediate sub command Features field D4h and cause the device to execute a self test W...

Page 143: ...r unique 1A to 1F9 Self test log 2 to 21 Each log data format is the same as that in byte 02 to 19 1FA 1FB Vendor unique 1FC Self test index 1FD 1FE Reserved 1FF Check sum Self test number Indicates the type of self test executed Self test execution status Same as byte 16Bh of the attribute value Self test index If this is 00h it indicates the status where the self test has never been executed Che...

Page 144: ...d 152h 1EBh Vender Unique 1Ech 1F3h Current LBA under test 1F4h 1F5h Current Span under test 1F6h 1F7h Feature Flags 1F8h Offline Execution Flag 1F9h Selective Offline Scan Number 1FAh 1FBh Vender Unique Reserved 1FCh 1FDh Selective Self test pending time min 1FEh 1FFh Checksum Test Span Selective self test log provides for the definition of up to five test spans If the starting and ending LBA val...

Page 145: ...ive test 2 Vendor specific unused 3 When set to one off line scan after selective test is pending 4 When set to one off line scan after selective test is active 5 15 Reserved Bit l shall be written by the host and returned unmodified by the device Bit 3 4 shall be written as zeros by the host and the device shall modify them as the test progress Selective Self test pending time min The selective s...

Page 146: ...d an aborted command error is posted FR field Command C0h DEVICE CONFIGURATION RESTORE C1h DEVICE CONFIGURATION FREEZE C2h DEVICE CONFIGURATION IDENTIFY C3h DEVICE CONFIGURATION SET 00h BFh C4h FFh Reserved At command issuance Shadow Block Registers setting contents CM 1 0 1 1 0 0 0 1 DH x x x x xx CH CL SN SC xx xx xx xx FR C0h C1h C2h C3h At command completion Shadow Block Registers contents to ...

Page 147: ...sued ST 51h ER 04h 3 The SET MAX ADDRESS EXT command F9h 37h has been specified with a value in the Host Protected Area ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h DEVICE CONFIGURATION FREEZE LOCK Features Field C1h The DEVICE CONFIGURATION FREEZE LOCK command prevents accidental modification of the Device Configuration Overlay settings After successful execution of a DEVICE ...

Page 148: ... reflected in IDENTIFY information When the bits in these words are cleared the device no longer supports the indicated command mode or feature set If a bit is set in the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit After execution of this command the settings are kept regardless of the power ...

Page 149: ...w are supported Bit 1 1 Ultra DMA mode 1 and below are supported Bit 0 1 Ultra DMA mode 0 is supported 3 to 6 Maximum LBA address Reflected in IDENTIFY information WORD60 61 WORD100 103 7 X 39CF Command set feature set supported Reflected in IDENTIFY information WORD82 87 Bits 15 14 Reserved Bit 13 1 SMART Conveyance self test supported Bit 12 1 SMART Selective self test supported Bit 11 1 FUA For...

Page 150: ...tification supported Bit 2 1 Interface power management supported Bit 1 1 Non zero buffer offsets in DMA Setup FIS supported Bit 0 1 Native command queuing supported 9 X 0000 Reserved for Serial ATA 10 to 254 X 0000 Reserved 255 X xxA5 Bits 15 8 Check sum code This is obtained by calculating the sum of all upper bytes and lower bytes in WORD 0 to 256 and the byte consisting of bits 7 to 0 in WORD ...

Page 151: ... of sectors in the partial block to be transferred is n where n remainder of number of sectors block count If the READ MULTIPLE command is issued when the READ MULTIPLE command is disabled the device rejects the READ MULTIPLE command with an ABORTED COMMAND error If an uncorrectable disk read error occurs the read operation stops at the sector where the error occurred even if the read operation ha...

Page 152: ...here read operations are allowed ST 51h ER 10h 2 The range where read operations are allowed will be exceeded by an address during a read operation ST 51h ER 10h 3 An uncorrectable disk read error occurred ST 51h ER 40h 4 The sync byte indicating the beginning of a sector was not found ST 51h ER 01h 5 The READ MULTIPLE command is disabled ST 51h ER 04h 6 A SATA communication error occurred ST 51h ...

Page 153: ...ount xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER End cylinder No MSB LBA End cylinder No LSB LBA End sector No LBA LSB 1 Error information 1 If the command is completed normally the number of remaining sectors is set in this field If the command is terminated because of an error the number of sectors for which data ha...

Page 154: ...ter a disk write operation has been attempted for the transferred blocks and partial block The write operation stops at the sector where the error occurred even if the write operation has not reached the end of the block At this time the number of remaining sectors the error sector and subsequent sectors and either cylinder head and sector addresses of the error sector CHS mode or the logical bloc...

Page 155: ...t sector No LBA LSB Transfer sector count xx R Retry At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this f...

Page 156: ...then enabled If the value of the Sector Count register is not a supported block count an ABORTED COMMAND error is posted and the READ MULTIPLE and WRITE MULTIPLE commands are disabled If the contents of the Sector Count field is 0 when the SET MULTIPLE MODE command is issued the READ MULTIPLE and WRITE MULTIPLE commands are disabled When the SET MULTIPLE MODE command operation is completed the dev...

Page 157: ...5 3 Host Commands C141 E224 5 83 At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx Sector count block Error information ...

Page 158: ... detected is transferred The device notifies the host of the status by sending the RegDH FIS At this time the number of remaining sectors including the sector where the error was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register The host system can select the DMA t...

Page 159: ...rt sector No LBA LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command is terminated due to an error the remaining number of sectors of which data was not transferred is set in this regis...

Page 160: ...ere the error was detected and either cylinder head and sector addresses CHS mode or the logical block address LBA mode of the sector where the error was detected are stored in the Shadow Block Register A host system can select the following transfer mode using the SET FEATURES command however the transfer speed does not change Multiword DMA transfer mode 0 to 2 Ultra DMA transfer mode 0 to 5 Erro...

Page 161: ...Start sector No LBA LSB Transfer sector count xx At command completion Shadow Block Registers contents to be read ST Status information DH x L x x HDNo LBA CH CL SN SC ER Start cylinder No MSB LBA Start cylinder No LSB LBA Start sector No LBA LSB 00 1 Error information 1 If the command was terminated because of an error the number of sectors for which data has not been written is set in this field...

Page 162: ... that the host system can read up to 512 bytes of data from the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 0 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx...

Page 163: ... are to be written In case a non recoverable disk write error has occurred while the data is being read the error generation address is put into the shadow block register before ending the command This error sector is deleted from the write cache data Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 ...

Page 164: ...tes of data is transferred from the host and the device writes the data to the buffer then reports the status Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information D...

Page 165: ...e host then sends the parameter information including a 512 byte date Table 5 25 shows the values of the parameter words and the meaning in the buffer Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 0 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers co...

Page 166: ...Identify Device command Error reporting conditions 1 A SATA communication error occurred ST 51h ER 0Ch At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 167: ...e 8 characters left 27 46 Set by a device Model name ASCII code 40 characters left 47 X 8010 Maximum number of sectors per block on READ WRITE MULTIPLE command 48 X 0000 Reserved 49 X 2F00 Capabilities 4 50 X 4000 Capabilities 5 51 X 0200 PIO data transfer mode 6 52 X 0200 Reserved 53 X 0007 Enable disable setting of words 54 58 and 64 70 88 7 54 Variable Number of current Cylinders 55 Variable Nu...

Page 168: ...Major version number 11 81 X 0021 Minor version number 82 X 346B Support of command sets 12 83 X 7F09 Support of command sets 13 84 X 60xx Support of command sets function 14 85 15 Valid of command sets function 15 86 16 Valid of command sets function 16 87 17 Default of command sets function 17 88 X xx3F Ultra DMA transfer mode 18 89 Set by a device Security Erase Unit execution time 1 LSB 2 min ...

Page 169: ... to 0 of word 0 to 254 and word 255 in byte units 1 Word 0 General configuration Bit 15 ATA device 0 ATAPI device 1 Bits 14 8 Undefined Bit 7 Removable disk drive 1 Bit 6 Fixed drive 1 Bits 5 3 Undefined Bit 2 IDENTIFY DEVICE Valid 0 Bits 1 0 Reserved 2 Word 1 3 6 60 61 Word MHV2120BH MHV2100BH MHV2080BH MHV2060BH MHV2040BH 1 X 3FFF X 3FFF X 3FFF X 3FFF X 3FFF 3 X 10 X 10 X 10 X 10 X 10 6 X 3F X 3...

Page 170: ...er value ATA spec is 1 Bit 12 Reserved Bit 11 1 IORDY supported Bit 10 1 IORDY inhibition supported Bit 9 1 DMA supported Bit 8 1 LBA supported Bits 7 0 Undefined 5 Word 50 Device capability Bit 15 0 Bit 14 1 Bit 13 to 1 Reserved Bit 0 Standby timer value 1 Standby timer value of the device is the smallest value 6 Word 51 PIO data transfer mode Bits 15 8 PIO data transfer mode X 02 PIO mode 2 supp...

Page 171: ... is selected Bits 7 3 Reserved Bit 2 1 Multiword DMA mode 2 1 and 0 supported Bit 1 0 1 Bit 1 1 Multiword DMA mode 1 and 0 supported Bit 0 1 Bit 0 1 Mode 0 10 Word 64 Advance PIO transfer mode support status Bits 15 8 Reserved Bits 7 0 Advance PIO transfer mode Bit 1 1 Mode 4 supported Bit 0 1 Mode 3 supported 11 WORD 75 X 001F 32 12 WORD 76 Bits 15 11 Reserved Bit 10 1 Supports the PHY event coun...

Page 172: ...erved 14 WORD 79 Bits 15 7 Reserved Bit 6 1 Enables the software settings preservation Bit 5 Reserved Bit 4 1 Enables the in order data delivery Bit 3 1 Enables the Power Management initiation function from Bit 2 1 Enables the Auto Activate optimization function in the DMA Setup FIS Bit 1 1 Enables the non zero buffer offset function in the DMA Setup FIS Bit 0 Reserved 15 WORD 80 Bits 15 8 Reserve...

Page 173: ...e PACKET command feature set Bit 3 1 Supports the power management feature set Bit 2 1 Supports the Removable Media feature set Bit 1 1 Supports the Security Mode feature set Bit 0 1 Supports the SMART feature set 17 WORD 83 Bit 15 0 Bit 14 1 Bit 13 1 Supports the FLUSH CACHE EXT command Bit 12 1 Supports the FLUSH CACHE command Bit 11 1 Supports the Device Configuration Overlay feature set Bit 10...

Page 174: ...it 7 1 Support the WRITE DMA QUEUED FUA EXT command Bit 6 1 Support the WRITE DMA FUA EXT and WRITE MULTIPLE FUA EXT commands Bit 5 1 Support the General Purpose Logging feature Bits 4 2 Reserved Bit 1 1 Supports the SMART SELF TEST Bit 0 1 Supports the SMART Error Logging 19 WORD 85 Bit 15 Undefined Bit 14 1 Supports the NOP command Bit 13 1 Supports the READ BUFFER command Bit 12 1 Supports the ...

Page 175: ...s WORD 83 Bit 5 1 Enables the Power Up In Standby function Bit 4 1 Enables the Removable Media Status Notification function Bit 3 1 Enables the Advanced Power Management function Bits 2 0 Same definition as WORD 83 21 WORD 87 Bit 15 0 The device always returns the fixed value indicated on the left Bit 14 1 The device always returns the fixed value indicated on the left Bits 13 0 Same definition as...

Page 176: ...lue FE C0 Performance mode BF 80 Acoustic mode 00 Acoustic management is unused it It is same as FE CO 25 WORD 100 103 When 48 bit LBA of the option customize is supported same number of LBA as WORD 60 61 is displayed 26 WORD 106 Bit 15 0 The device always returns the fixed value indicated on the left Bit 14 1 The device always returns the fixed value indicated on the left Bit 13 1 Each device has...

Page 177: ...en error bit is set is enabled The drive doesn t execute the dummy transferring 0 Clearing DRQ bit to zero when error bit is set is disabled The drive executes the dummy transferring 29 WORD 128 Bits 15 9 Reserved Bit 8 Security level 0 High 1 Maximum Bits 7 6 Reserved Bit 5 1 Enhanced security erase supported Bit 4 1 Security counter expired Bit 3 1 Security frozen Bit 2 1 Security locked Bit 1 1...

Page 178: ...ata transfer mode 1 X 04 Enables the automatic reassign Note 1 X 05 Enables the advanced power management function 2 X 06 Enables the Power Up In Standby function Note 1 X 07 Spin up the Power Up In Standby status device Note 1 X 10 Enables the Serial ATA function 3 X 33 Undefined Note 1 X 42 Enables the Acoustic management function 4 X 54 Undefined Note 1 X 55 Disables the read cache function X 5...

Page 179: ... is a response to the command nothing is done Note 2 Although there is a response to the command and this command reflects on Identify Device information DRQ bit is always cleared to zero when error is occurred in PIO read command This drive always doesn t the dummy transferring At power on the default mode is set as follows Write cache function Enabled Transfer mode PIO Mode 4 Multiworld DMA Mode...

Page 180: ...ata Transfer Mode The host sets X 03 to the Features field By issuing this command with setting a value to the Sector Count field the transfer mode can be selected Upper 5 bits of the Sector Count register defines the transfer type and lower 3 bits specifies the binary mode value The IDD supports following values in the Sector Count field value If other value than below is specified an ABORTED COM...

Page 181: ...100 X 44 Mode 4 Ultra DMA transfer mode X 01000 101 X 45 Mode 5 2 Advanced Power Management APM The host writes the Sector Count field with the desired power management level and executes this command with the Features field X 05 and then Advanced Power Management is enabled The drive automatically shifts to power saving mode up to the specified APM level when the drive does not receive any comman...

Page 182: ...tor Count field Serial ATA function Sector Count field Non zero buffer offset in DMA Setup FIS 01h 1 DMA Setup FIS Auto Activate optimization 02h 2 Device initiated interface power state Transitions 03h 3 Guaranteed In Order Data Delivery 04h 1 Asynchronous Notification 05h 1 Software Settings Preservation 06h 4 1 The device normally responds to the command but performs no operation 2 This feature...

Page 183: ...el setting is preserved by the drive across power on and COMRESET AAM Level Sector Count Filed Performance mode Fast Seek Acoustic mode Slow Seek Abort Non Operate C0h FEh 80h BFh 01h 7Fh 00h FFh High speed seek to which gives priority to the performance operates as for Performance mode and low speed seek by which the seek sound is suppressed operates as for Acoustic mode Setting the seek mode by ...

Page 184: ...word version number This value is valid only when Word 0 Bit 0 is set to one 18 to 255 Reserved Table 5 28 Relationship between combination of Identifier and Security level and operation of the lock function Identifier Level Description User High The specified password is set as a new user password The lock function is enabled after the device is turned off and then on LOCKED MODE can be canceled ...

Page 185: ...Frozen mode ST 51h ER 04h 3 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 186: ...ssword is compared with the user password already set If the passwords are the same LOCKED MODE is canceled Otherwise the Aborted Command error is returned If the password comparison fails the device decrements the UNLOCK counter The UNLOCK counter initially has a value of five When the value of the UNLOCK counter reaches zero this command or the SECURITY ERASE UNIT command causes the Aborted Comm...

Page 187: ...5 3 Host Commands C141 E224 5 113 At command completion Shadow Block Register contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 188: ...erased unnecessarily by the SECURITY ERASE UNIT command Error reporting conditions 1 The device is in Security Frozen mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 0 1 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information D...

Page 189: ...is command invalidates the user password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password Error reporting conditions 1 An incorrect password is specified ST 51h ER 04h 2 The Security Erase Prepare command did not complete normally beforehand ST 51h ER 04h 3 The device is in Security Frozen mode ST 51h ER 04h 4 A SATA...

Page 190: ... is canceled when the power is turned off If this command is reissued in FROZEN MODE the command is completed and FROZEN MODE remains unchanged The following medium access commands return the Aborted Command error when the device is in LOCKED MODE READ DMA EXT READ MULTIPLE EXT READ SECTORS EXT READ VERIFY SECTORS EXT WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTORS EXT WRITE VERIFY SECURITY DISABLE...

Page 191: ...The device is in Security Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 192: ...r password the master password is retained To recover the master password issue the SECURITY SET PASSWORD command and reset the user password If the user password or master password transferred from the host does not match the Aborted Command error is returned Issuing this command while in LOCKED MODE or FROZEN MODE returns the Aborted Command error The section about the SECURITY FREEZE LOCK comma...

Page 193: ...he device is in Security Frozen mode ST 51h ER 04h 4 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 0 1 1 0 DH x x x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER xx xx xx xx Error information ...

Page 194: ...L and SN field Then reports the status to the host system Error reporting conditions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 0 DH x L x x xx CH CL SN SC FR xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x Max head LBA MSB CH CL SN SC ER CYL No MSB...

Page 195: ...alue set by this command is held even after power on When the VV bit is 0 the value set by this command becomes invalid when the power is turned on and the maximum address returns to the value most lately set when VV bit 1 When the command with VV 1 has not issued before the maximum address returns to the default value When the READ NATIVE MAX ADDRESS command has been issued immediately preceding ...

Page 196: ...uance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x L x x HD No LBA CH CL SN CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB SC xx VV FR xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH CL SN SC ER CYL No MSB LBA CYL No LSB LBA SCT No LBA LSB xx Error information SET MAX SET PASSWORD Features Field 01h This command requests a...

Page 197: ...occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 01 At command completion Shadow Block Registers contents to be read ST Status information DH CH CL SN SC ER xx xx xx xx xx Error information Password information Words Contents 0 Reserved 1 to 16 Password 32 bytes 17 to 255 Reserved ...

Page 198: ...X LOCK state until a power cycle or the acceptance of SET MAX UNLOCK or SET MAX FREEZE LOCK command Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 02 At command comp...

Page 199: ... When this counter reaches zero then SET MAX UNLOCK command returns command aborted until a power cycle If the password compare matches then the device makes a transition to the Set Max Unlocked state and all SET MAX commands will be accepted Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 The device is in Set Max Unlocked mode ST 51h...

Page 200: ...ADDRESS SET MAX SET PASSWORD SET MAX LOCK SET MAX UNLOCK SET MAX FREEZE LOCK Error reporting conditions 1 The device is in Set Max Locked mode or Set Max Freeze Locked mode ST 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 1 1 0 0 1 DH x x x x xx CH CL SN SC FR xx xx xx xx 04 At command completion Shadow Block Reg...

Page 201: ...s 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command complet...

Page 202: ...ommand was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ DAM command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Blo...

Page 203: ... 51h ER 04h 2 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 0 0 1 0 0 1 1 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER Native max address ...

Page 204: ...The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 0 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion ...

Page 205: ...g address 10h For the data format of Read Log Ext log page 10h see Table 5 30 The events of the PHY level on an interface are collected and it registers with Read Log Extend page 11h This Read Log Ext log page can be read by specifying Sector offset 00h Sector count 01h and Log address 11h For the data format of Read Log Ext log page 11h see Table 5 32 If this command is not supported or if an inv...

Page 206: ...CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 207: ...lue 07 Dev Head field value 08 Sector Number Exp field value 09 Cylinder Low Exp field value 0A Cylinder High Exp field value 0B Reserved 0C Sector Count field value 0D Sector Count Exp field value 0E to FF Reserved 100 to 1FE Vendor Unique 1FF Check sum Table 5 31 Tag field information Bit Description 0 4 If bit 7 is 0 this field has an error tag number 5 6 Reserved 7 If this bit is 0 the field c...

Page 208: ... in the page 1 Command failed due to an ICRC error 2 Data FIS R_ERR ending status transmitted and received 3 Data FIS R_ERR ending status transmitted 4 Data FIS R_ERR ending status received 5 Non data FIS R_ERR ending status transmitted and received 6 Non data FIS R_ERR ending status transmitted 8 Non data FIS retries transmitted 9 Transitions from drive PhyRdy to drive PhyNRdy A Signature Device ...

Page 209: ...ns 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command compl...

Page 210: ...command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE DMA command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 0 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow B...

Page 211: ...VV bit 1 When the command with VV 1 has not issued before the maximum address returns to the default value After power on the host can issue this command only once when VV bit 1 If this command with VV bit 1 is issued twice or more any command following the first time will result in an ID Not Found error When the SET MAX ADDRESS EXT command is executed SET MAX ADDRESS command is aborted The addres...

Page 212: ...X LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx SC xx VV FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER SET MAX LBA 47 40 SET MAX LBA 23 16 SET MAX LBA 39 32 SET MAX LBA 15 8 SET MAX LBA 31 24 SET MAX LBA 7 0 xx xx Error information ...

Page 213: ...ns 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the WRITE MULTIPLE command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 0 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command compl...

Page 214: ...or Sector offset the Aborted Command error occurs Error reporting conditions 1 An error was detected during power on processing ST 51h ER 04h 2 An error was detected during wake up processing in cases where wake up processing is required before execution of this command ST 51h ER 04h 3 A write fault was detected while the write cache was disabled ST 71h ER 10h 4 While the write cache is enabled if...

Page 215: ...EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx Sector offset 15 8 Sector offset 7 0 xx Log address Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH x x x x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information ...

Page 216: ...ions 1 The command was issued in CHS mode ST 51h ER 04h The other error reporting conditions are the same as those of the READ VERIFY SECTOR S command At command issuance Shadow Block Registers setting contents CM 0 1 0 0 0 0 1 0 DH 1 L 1 x Xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At comma...

Page 217: ...tions 1 A SATA communication error occurred ST 51h ER 14h At command issuance Shadow Block Registers setting contents CM 1 1 1 0 1 0 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR xx xx xx xx xx xx xx xx xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx E...

Page 218: ...ame as those of the WRITE MULTIPLE EXT command At command issuance Shadow Block Registers setting contents CM 1 1 0 0 1 1 1 0 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH C...

Page 219: ...same as those of the WRITE DMA EXT command At command issuance Shadow Block Registers setting contents CM 0 0 1 1 1 1 0 1 DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC FR EXP FR LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 Sector count 15 8 Sector count 7 0 xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EX...

Page 220: ...SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reads data from media regardless of whether the data requested by the ho...

Page 221: ... xx CH EXP CH CL EXP CL SN EXP SN SC EXP LBA 47 40 LBA 23 16 LBA 39 32 LBA 15 8 LBA 31 24 LBA 7 0 xx SC TAG xx FR EXP FR xx xx At command completion Shadow Block Registers contents to be read ST Status information DH 1 L 1 x xx CH EXP CH CL EXP CL SN EXP SN SC EXP SC ER xx xx xx xx xx xx xx xx Error information FUA If this bit is 1 the device always reports the status after data is written to a me...

Page 222: ...XECUTE DEVICE DIAGNOSTIC V 1 1 1 1 INITIALIZE DEVICE PARAMETERS V V V V V DOWNLOAD MICROCODE V V V V V STANDBY IMMEDIATE V V V V V IDLE UNLOAD IMMEDIATE V V V V V STANDBY V V V V V IDLE V V V V V CHECK POWER MODE V V V V V SLEEP V V V V V SMART V V V V V V V DEVICE CONFIGURATION V V V V V V READ MULTIPLE V V V V V V V WRITE MULTIPLE V V V V V V SET MULTIPLE MODE V V V V V READ DMA V V V V V V V WR...

Page 223: ...AD DMA EXT V V V V V V V READ NATIVE MAX ADDRESS EXT V V V V V READ MULTIPLE EXT V V V V V V V WRITE LOG EXT V V V V V V WRITE SECTOR S EXT V V V V V V WRITE DMA EXT V V V V V V SET MAX ADDRESS EXT V V V V V V WRITE MULTIPLE EXT V V V V V V READ LOG EXT V V V V V V V READ VERIFY SECTOR S EXT V V V V V V V FLUSH CACHE EXT V V V V V V WRITE MULTIPLE FUA EXT V V V V V V WRITE DMA FUA EXT V V V V V V ...

Page 224: ...to as follows in this section FIS Frame Information Structure type Abbreviation Register Host to Device RegHD Register Device to Host RegDH DMA Active Device to Host DMA Active DMA Setup Device to Host or Host to Device Bidirectional DMA Setup Set Device Bits Device to Host SetDB BIST Active Bidirectional BIST Active PIO Setup Device to Host PIO Setup Data Host to Device or Device to Host Bidirect...

Page 225: ...PREPARE SECURITY FREEZE LOCK FLUSH CACHE EXT SLEEP DEVICE CONFIGRATION RESTORE FREEZE LOCK The following is the protocol for command execution without data transfer 1 The device receives a non data command with the RegHD FIS 2 The device executes the received command 3 Command execution is completed 4 The device reports the completion of command execution by sending to the host the RegDH FIS with ...

Page 226: ...ents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to send data it sets 0 in the BSY bit 1 in the DRQ bit and 1 in the I bit of the Status field of the PIO Setup FIS then sends this FIS to the host At this time if the requested data is read from the last sector to be processed the device sets 0 in both the BSY bit and DRQ bit of the E_Status fi...

Page 227: ...g commands involves data transfers from the host system to the device WRITE SECTOR S EXT WRITE MULTI EXT FUA EXT WRITE BUFFER WRITE VERIFY SMART WRITE LOG SECTOR SECURITY DISABLE PASSWORD SECURITY ERASE UNIT SECURITY SET PASSWORD SECURITY UNLOCK DOWNLOAD MICROCODE WRITE LOG EXT DEVICE CONFIGRATION SET Data of one or more sectors is transferred from the host to the device ...

Page 228: ... a data transfer to the first sector while it sets 1 in the I bit for a data transfer to any sector other than the first sector Then it sends this FIS to the host In the E_Status field the device sets 1 in the BSY bit and 0 in the DRQ bit 4 The device receives the DATA FIS from the host 5 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete executio...

Page 229: ...ce receives a DMA data in command with the RegHD FIS 2 If an error remaining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to send data it sends the Data FIS to the host 4 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If any data remains to b...

Page 230: ...2 If an error remaining in the device prevents command execution the device sends the RegDH FIS with 1 set in the I bit 3 When the device is ready to receive data it sends the DMA Active FIS to the host 4 The device receives the Data FIS from the host 5 When all data has been transferred the device sends the RegDH FIS with 1 set in the I bit to complete execution of the command If any data remains...

Page 231: ...d in the SetDB FIS corresponding to the tag number of the completed command is set by the device and the device sets 0 in the Err bit and 0 in the Error register in the Set Device Bits FIS Then it sends the Set Device Bits FIS to the host 5 For the data transfer of the WRITE FP DMA QUEUED command if the DMA Setup Auto Activate function is disabled the device sends to the host the DMA Setup FIS wit...

Page 232: ...set and COMRESET The device reports abort for other commands 10 If the device receives the READ LOG EXT command with page 10h specified queued commands are aborted Then after the device sends to the host the SetDB FIS ERR 0 ERRReg 0 I 0 and SActive 0xFFFFFFFF it sends to the host the log data for the READ LOG EXT command with page 10h specified and reports the status of this command Next the comma...

Page 233: ...5 4 Command Protocol C141 E224 5 159 Device Host RegHD RegDH DMA Setup SetDB DATA DMACT Figure 5 19 WRITE FP DMA QUEUED command protocol ...

Page 234: ...A interface is established the host sets 0xFFh in the Status field of the Shadow Block Register The device completes the power on sequence within 10 ms so that communication with the SATA interface can be established Device TX Host RX Host TX Device RX Host power on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device rel...

Page 235: ...st TX Device RX Host device on Host ComReset Host releases ComReset Host calibrate Host ComWake Host releases ComWake Host Align Host data Device ComInit Device releases ComInit Device Calibrate Device ComWake Device Align Device data Figure 5 21 COMRESET sequence ...

Page 236: ...This page is intentionally left blank ...

Page 237: ...6 1 CHAPTER 6 Operations 6 1 Reset and Diagnosis 6 2 Power Save 6 3 Power Save Controlled by Interface Power Management IPM 6 4 Read ahead Cache 6 5 Write Cache This chapter explains each of the above operations ...

Page 238: ...s After communication with the SATA interface is established the host sets 0xFFh in the Status field of the Shadow Block The device establishes communication with the SATA interface PHY Ready within 10 ms The device sends the FIS STS 50h to notify the host that the device is ready Note Figure 6 1 assumes that power is turned on after the power off state continued for more than five seconds Figure ...

Page 239: ...6 1 Reset and Diagnosis C141 E224 6 3 Figure 6 2 Response to power on when the device is powered on earlier than the host ...

Page 240: ...as the response when power is turned on and a power on reset is then cancelled The device establishes communication with the SATA interface PHY Ready and sends the RegDH FIS STS 50h to notify the host that the device is ready Then the COMRESET sequence is completed Figure 6 3 Response to COMRESET ...

Page 241: ...code of 06h refer to Section 5 3 2 28 If a device supports software settings preservation the feature shall be enabled by default 6 1 2 2 COMRESET preservation requirements The software settings that shall be preserved across COMRESET are listed below The device is only required to preserve the indicated software setting if it supports the particular feature command the setting is associated with ...

Page 242: ...mand code of 03h SET FEATURES Advanced Power Management Enable Disable The advanced power anagement enable disable setting established by the SET FEATURES command with subcommand code of 05h or 85h The advanced power management level established in the Sector Count field when advanced power management is enabled SET FEATURES subcommand code 05h shall also be preserved SET FEATURES Read Look Ahead ...

Page 243: ...to a software reset When a software reset is accepted the device performs a self diagnosis and it sends the RegDH FIS STS 50h to notify the host that the device is ready Then the software reset sequence is completed Figure 6 4 Response to a software reset ...

Page 244: ... mode In this mode all the electric circuit in the device are active or the device is under seek read or write operation A device enters the active mode under the following conditions The media access system is received 2 Active idle mode In this mode circuits on the device is set to power save mode The device enters the Active idle mode under the following conditions After completion of the comma...

Page 245: ...has elapsed in the low power idle state APM Mode 2 The time specified by the STANDBY or IDLE command has elapsed after completion of the command A reset is issued in the sleep mode When one of following commands is issued the command is executed normally and the device is still stayed in the standby mode Reset hardware or software STANDBY command STANDBY IMMEDIATE command INITIALIZE DEVICE PARAMET...

Page 246: ...Operations 6 10 C141 E224 6 2 2 Power commands The following commands are available as power commands IDLE IDLE IMMEDIATE STANDBY STANDBY IMMEDIATE SLEEP CHECK POWER MODE SET FEATURES APM setting ...

Page 247: ...he period in which the device must switch to Active mode from the Interface Power Down state Period in which the device must switch to Active mode Partial mode Maximum 10 µs Slumber mode Maximum 10 ms 1 Active mode The interface is in the Active state and commands can be accepted 2 Partial mode In this mode shallow Power Save mode is set for the interface circuit The device switches to Partial mod...

Page 248: ...nd responds with the PMACK signal The device sends the PMREQ_S signal and the host responds with PMACK signal The device cannot switch to Slumber mode if the following condition is satisfied The device responds with the PMNAK signal because it is not waiting for commands The device returns to Active mode from Slumber mode when the following condition is satisfied The device receives the COMRESET o...

Page 249: ...ssing the disk media As the result faster data access becomes possible for the host 6 4 1 Data buffer structure This device contains a data buffer This buffer is divided into two areas one area is used for MPU work and the other is used as a read cache for another command See Figure 6 5 8 MB buffer For MPU work For R W command 8 192 KB 8 388 608 bytes 512 KB 524 288 bytes 7 680 KB 7 864 320 bytes ...

Page 250: ... the caching function is prohibited by the SET FEATURES command the caching operation is not performed 2 Data that is a target of caching The data that is a target of caching are as follows 1 Read ahead data that is read from disk media and saved to the data buffer upon completion of execution of a command that is a target of caching 2 Pre read data that is read from disk media and saved to the da...

Page 251: ...TRACK SET FEATURES SECURITY ERASE UNIT DEVICE CONFIGURATION DOWNLOAD MICROCODE UNSUPPORT COMMAND INVALID COMMAND 1 2Commands that partially invalidate caching data READ DMA READ MULTIPLE READ SECTOR S READ DMA EXT READ MULTIPLE EXT READ SECTOR S EXT READ FP DMA QUEUED WRITE DMA WRITE MULTIPLE WRITE SECTOR S WRITE DMA EXT WRITE MULTIPLE EXT WRITE SECTOR S EXT WRITE DMA FUA EXT WRITE MULTIPLE FUA EX...

Page 252: ...AP is set at the requested data reading position Read segment HAP host address pointer DAP disk address pointer 2 During reading of read requested data the request data that has already been read is sent to the host system Read requested data Free space HAP DAP Read requested data is stored until this point 3 When reading of read requested data is completed and transfer of the read requested data ...

Page 253: ... read requested data the request data that has already been read is sent to the host system Cache valid data Free space Read requested data DAP disk address pointer HAP host address pointer 3 When reading of read requested data is completed and transfer of the read requested data to the host system is completed the read ahead operation continues until a certain amount of data is stored Read ahead ...

Page 254: ... while the read ahead operation is in progress 1 An example is the state shown below where the previous read command is executing sequential reading First HAP is set at the location where hit data is stored HAP It is reset to the hit data location for transfers HAP end location of the previous read command DAP end location of the previous read command Cache data Full hit data Cache data HAP DAP 2 ...

Page 255: ...valid data START LBA LAST LBA 1 HAP is set at the address where partial hit data is stored and Transfer is started Cache valid data Partial hit data HAP host address pointer 2 DAP and HAP are set at the head of Buffer newly allocated and insufficient data is read Read segment HAP host address pointer DAP disk address pointer 3 When reading the read requested data ends and the transmission of the r...

Page 256: ...rmed when the caching function is prohibited by the SET FEATURES command 2 Invalidation of cached data If an error occurs during writing onto media write processing is repeated up to as many times as specified for retry processing If retry fails for a sector because the retry limit is reached automatic alternate sector processing is executed for the sector If the automatic alternate sector process...

Page 257: ...RESET or software reset is received while cached data is stored on the data buffer data of the data buffer is written on the media and reset processing is then performed This is true for both a hard reset and soft reset 6 Cashing function when power supply is turned on The cashing function is invalid until Calibration is done after the power supply is turned on about 10 sec It is effective in Defa...

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Page 259: ...these parameters The BIOS of a PC AT cannot make full use of the physical specifications of these drivers To make the best use of these drives a BIOS that can handle the standard parameters of these drives is required Command Commands are instructions to input data to and output data from a drive Commands are written in command registers Connector Connector Plug Host system side It means a host re...

Page 260: ...on time total power on time by the number of failures in the disk drive during operation MTTR Mean time to repair The MTTR is the average time required for a service person to diagnose and repair a faulty drive PIO Programmed input output Mode to transfer data under control of the host CPU Positioning Sum of the seek time and mean rotational delay Power save mode The power save modes are idle mode...

Page 261: ...rrent Parallel ATA physical storage interface The parallel data transfer of Parallel ATA is changed to the serial data transfer in Serial ATA for obtaining greater data transfer speed Slave Device 1 The slave is a second drive that can operate on the AT bus The slave is daisy chained with the first drive operating in conformity with the ATA standard Status The status is a piece of one byte informa...

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Page 263: ...ve write fault E ECC Error checking and correction ER Error field ERR Error EU European Union F FR Feature field H HA Host adapter HDD Hard disk drive I IDNF ID not found IRQ14 Interrupt request 14 L LED Light emitting diode M MB Mega byte MB S Mega byte per seconds MPU Micro processor unit P PCA Printed circuit assembly PIO Programmed input output R RLL Run length limited RoHS The Restrictions of...

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Page 265: ...for 6 14 6 20 data for 6 14 caching data invalidating 6 15 caching operation 6 14 capability off line data collection 5 64 cashing function at power on 6 21 caution handling 3 7 CHECK POWER MODE 5 53 checksum 5 65 5 67 5 69 circuit controller 2 3 read write 2 3 circuit configuration 4 3 4 5 circulation filter 2 2 CN1 3 10 code command 5 29 5 148 diagnostic 5 43 command code 5 29 5 148 command code...

Page 266: ...ice configuration 2 1 2 2 DEVICE CONFIGURATION 5 72 DEVICE CONFIGURATION FREEZE LOCK 5 73 DEVICE CONFIGURATION IDENTIFY 5 74 DEVICE CONFIGURATION IDENTIFY data structure 5 75 5 76 DEVICE CONFIGURATION RESTORE 5 73 DEVICE CONFIGURATION SET 5 74 device connector 3 9 device control field 5 28 device overview 1 1 device ready DRDY bit 5 27 device seek complete DSC bit 5 27 device specification 1 4 dev...

Page 267: ...reshold value data format of 5 60 H handling caution 3 7 head 2 2 high resistance against shock 1 3 high speed transfer rate 1 2 HIPM 1 15 hit full 6 17 partial 6 19 sequential 6 17 host command 5 29 host system connection 3 9 host system connector specification 3 10 host initiated interface power management 1 15 host initiated power management interface 1 15 hot plug 5 13 I ID attribute 5 61 iden...

Page 268: ...and signaling 5 4 outer guard band 4 15 outerview disk drive 2 2 outline 4 2 outline of frame information structure FIS 5 17 shadow block register 5 16 P P11 function 5 11 PAD 4 17 parameter 5 29 5 148 partial hit 6 19 partial mode 6 11 password master 5 112 user 5 112 physical Interface 5 2 physical sector servo configuration on disk surface 4 16 pinout connector 5 10 PIO data in command protocol...

Page 269: ...tent of 5 118 SECURITY SET PASSWORD 5 110 SECURITY SET PASSWORD data contents of 5 110 SECURITY UNLOCK 5 112 SEEK 5 42 seek operation 4 18 selective self test feature flag 5 71 selective self test log data structure 5 70 selective self test pending time min 5 71 self calibration 4 7 self calibration content 4 7 self diagnosis 1 3 self test execution status 5 63 5 69 self test index 5 69 self test ...

Page 270: ...easurement point 3 6 surface temperature standard value 3 6 system configuration 2 3 T tag field information 5 133 5 134 temperature ambient 3 6 test span 5 70 theory of device operation 4 1 total number of drive error 5 67 track following operation 4 18 U UNLOAD IMMEDIATE 5 48 unrecoverable read error 1 12 user password 5 112 using read segment buffer 6 16 V VCM current sense resistor CSR 4 14 vi...

Page 271: ...G Good F Fair P Poor General appearance Technical level Organization Clarity Accuracy Illustration Glossary Acronyms Abbreviations Index Comments Suggestions List any errors or suggestions for improvement Page Line Contents Please send this form to the address below We will use your comments in planning future editions Address Fujitsu Learning Media Limited 37 10 Nishikamata 7 chome Oota ku Tokyo ...

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Page 273: ...MHV2120BH MHV2100BH MHV2080BH MHV2060BH MHV2040BH DISK DRIVES PRODUCT MANUAL C141 E224 02EN MHV2120BH MHV2100BH MHV2080BH MHV2060BH MHV2040BH DISK DRIVES PRODUCT MANUAL C141 E224 02EN ...

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