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The DSPI Status Register (SR) contains both flags and information about the current status of the
module. It’s fields are:
TCF: Transfer complete flag, this flag is raised once the last incoming data of a frame is
sampled and before
𝑡
𝐴𝑆𝐶
delay is started.
TXRXS: TX and RX status, when 0, TX/RX operations are disabled and DSPI is in
STOPPED state.
EOQF: End of queue flag, indicated that the ongoing transmission is the last entry in a
queue. This flag can be raised by writing 1 to the EOQ bit in the command field of a TX
FIFO. (see following section.)
TFUF: Transmit FIFO underflow flag, in a slave mode DSPI module, is set when the TX
FIFO is empty and an external master initiated a transfer.
TFFF: Transmit FIFO fill flag, when set, it means that the TX FIFO can be filled with more
entries.
RFOF: Receive FIFO overflow flag, indicates that RX FIFO is full and a transfer is initiated.
RFDF: Receive FIFO drain flag, indicated that there are data in RXFIFO that can be read.
TXCTR/RXCTR: indicates the number of entries in the TX/RX FIFO.
TXTNXTPTR: Transmit next pointer, indicates which TX FIFO entry will be transmitted
on the next transfer.
POPNXTPTR: POP next pointer, indicates which RX FIFO entry will be read on the next
read.
And the DSPI Interrupt Request Enable Register (RSER) can be used to enable interrupts related
to the previous flags, this registers has the following enable fields: TCF_RE, EOQF_RE, TFUF_RE,
TFFF_RE, RFOF_RE and RFDF_RE. Each of these interrupts has a different ISR vector, so a
different handler.
2.5.
Transmit/Receive Registers
In DSPI module, transmitting and receiving data are done using a PUSH and a POP register for
writing to TX FIFO and reading from RX FIFO.
Figure 96 : DSPI Push TX FIFO Register (R.M. Rev8 –Fig. 23-8)
The DSPI PUSH TX FIFO Register (PUSHR) is made of a 16-bit command field and a 16-bit data
field called TXDATA. TXDATA contains the data to be transmitted and the command field is
made of various sub-fields to configure the transfer.
Summary of Contents for MPC5604B
Page 1: ...LAAS CNRS Quick Start to MPC5604B Embedded Development Sahin Serdar 21 06 2013...
Page 31: ...Figure 33 INTC SW HW mode comparison Freescale Tutorial...
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