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Freescale Semiconductor MPC5604B, Quick Start Manual

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There’s also a glitch filter for these pads that avoids erroneous requests that may be triggered by 
noise. Interrupt Filter Enable Register (IFER) can set which pads are to be filtered. And IFMC 
and IFCPR are used to set filters parameters.  These two registers together have only two fields 
MAXCNT[x][3:0] (x: one for each pad) is the Maximum Couter, IFCP[3:0] is the clock prescaler 
setting common to all pads. Having these two parameters, we have: 

Filter Period[

𝑥

] =

𝑇

𝐶𝐾

× (

𝑀𝐴𝑋𝐶𝑁𝑇

[

𝑥

] +

𝑛

)  (

𝑛

 is random in [

−

1,3]) 

𝑇

𝐶𝐾

= (

𝐼𝐹𝐶𝑃

+ 1) ×

𝑇

𝐹𝐼𝑅𝐶

,   

𝑓

𝐹𝐼𝑅𝐶

= 16

𝑀𝐻𝑧

 

If the signal is steady for at least the Filter Period, then the glitch filter triggers the interrupt. 

Summary of Contents for MPC5604B

Page 1: ...LAAS CNRS Quick Start to MPC5604B Embedded Development Sahin Serdar 21 06 2013...

Page 2: ...2 3 Sysclk 10 2 4 FMPLL 11 3 A device initialisation procedure 13 4 SWT Software Watchdog Timer 14 Chapter 2 SIUL System Integration Unit Line 15 1 Introduction 15 2 Pad configuration 15 3 GPIO Genera...

Page 3: ...MCB Modulus Counter Buffered 41 1 10 OPWFMB Output Pulse Width and Frequency Modulation Buffered 41 1 11 OPWMCB Center Aligned Output Pulse Width Buffered 43 1 12 OPWMB Output Pulse Width Modulation B...

Page 4: ...troduction 66 1 1 SPI Protocol Description 66 1 2 Module Presentation 68 2 Configuration 69 2 1 Signal Configuration 69 2 2 Module Configuration Register 69 2 3 Transfer Configuration Register 70 2 3...

Page 5: ...Driver for a terminal interface 88 5 1 System initialisation 88 5 2 SIUL configuration 88 5 3 ADC configuration 89 5 4 eMIOS configuration 90 5 5 Main procedure and use of the driver 90 5 6 Results 9...

Page 6: ...sters 111 7 4 Status and Interrupt Registers 113 8 FlexCAN usage explained with an example 115 8 1 Initialisation 116 8 2 Transmission 116 8 3 Reception 117 8 4 Interrupt Handling 117 9 CAN Transceive...

Page 7: ...e focused on the configuration and use of those peripherals by summarizing the official reference manual but it also gives commented code examples and tips for overcoming common difficulties Our tests...

Page 8: ...often the same structure first it initialises the system clock and mode and then it initialises and configures each peripheral it uses On this MCU it also has to disable the watchdog before doing anyt...

Page 9: ...For instance when using the UART pins on the port B you should check if the jumpers connecting those pins to the LIN Transceiver are removed Otherwise you would receive framing errors MPC5604B C Data...

Page 10: ...s active after a system reset or a non recoverable failure The device leaves this state once the reset sequence that initialises the chip and power is completed The system clock is set to the internal...

Page 11: ...bedded software with no power saving specifications we will only need configuring RUN0 3 Figure 3 Mode Configuration Register for RUN 0 3 Reference Manual Rev8 Fig 8 13 Quick explanation of modifiable...

Page 12: ...PPC 7 Figure 5 Low Power Peripheral Configuration Registers Reference Manual Rev8 Fig 8 22 Once all the possible modes have been selected using these 8 8 registers each one of the 144 peripherals can...

Page 13: ...ipherals Reference Manual Rev8 Fig 6 1 1 5 Device mode selection After enabling modes we want to use configuring them and the peripherals we can change the current mode of the device using the Mode Co...

Page 14: ...al clocks in this microcontroller The clocking structure is represented on the figure below Figure 10 The Clock Architecture MC_CGM Freescale Lecture There are three sets of peripherals in this archit...

Page 15: ...saving We can also generate an output clock from pin PA 0 called CLOCK OUT using these fast oscillators 2 2 Clock Out In this section we will review the registers used to generate an output clock It...

Page 16: ...o 1 and the clock is ready to be used The clock is divided by DIVCLOK 1 Other clock sources control register are similar with some different features RC oscillators can be trimmed by the software to i...

Page 17: ...F This module has the following constraints FXOSC 4MHz 16MHz VCO 256MHz 512MHz NDIV 32 96 IDF 1 15 ODF 2 4 8 16 PHI 64MHz After carefully choosing values for NDIV IDF and ODF using a spread sheet for...

Page 18: ...e can also modulate the clock using frequency modulation with a triangular wave This will help reduce the effects of electromagnetic interference generated by the high frequency harmonics caused aroun...

Page 19: ...PERIOD and INC_STEP have to be calculated using selected values of and in order to respect the following limitation _ _ 215 1 Recommended modulation depths are 0 25 to 4 for center spread and 0 5 to 8...

Page 20: ...n the debug mode Using its configuration registers this module is highly customisable for better fault detection for more details see the chapter 30 of the reference manual rev 8 especially the paragr...

Page 21: ...rocess external interrupts that can be triggered on rising falling edges On TRK MPC5604B there are 123 pads with GPIO functionality and 16 with external interrupt ability 2 Pad configuration This func...

Page 22: ...when this bit is 0 pad is configured for push pull output and when it is 1 pad is an open drain output SRC Slew Rate Control by default 0 the pad is slow and writing 1 makes it configured as medium o...

Page 23: ...lity allows reading and writing binary values on pins 0V 5V To set or clear a pad we need to use GPIO Pad Data Output register Figure 24 GPIO Pad Data Output Register Reference Manual Rev7 Fig 8 12 Th...

Page 24: ...ly change pads of interest there are masked parallel registers which simplifies this problem see figure below This extract of code will blink LEDs 1 to 4 sequentially while the button S1 is pressed ui...

Page 25: ...ctors spared for EIRQ pins IRQ0 for EIRQ 0 7 and IRQ2 for EIRQ 8 15 Looking at the diagram above we can identify following registers Interrupt Request Enable Register IRER with a 16 bit field to speci...

Page 26: ...IFMC and IFCPR are used to set filters parameters These two registers together have only two fields MAXCNT x 3 0 x one for each pad is the Maximum Couter IFCP 3 0 is the clock prescaler setting common...

Page 27: ...nterrupt Service Requests ISR management In software vector mode2 ISRs coming from peripherals trigger IVOR4 exceptions This exception branches to INTC handling functions which saves current register...

Page 28: ...upts software ISR and the other 134 are hardware ISR linked to the peripherals Each of these vectors can be given a priority between 0 and 15 the latter being the highest priority An interruption of h...

Page 29: ...tor Table handlerFn is a void function written by the user and psrPriority is the priority between 0 and 15 0 priority is not served Example Blinking a LED when PIT1 a timer see following chapters int...

Page 30: ...r priority interrupt is triggered while a lower priority is being processed When nested interrupts are enabled a higher priority interrupt can pause the handler of a lower priority and finish it up la...

Page 31: ...Figure 33 INTC SW HW mode comparison Freescale Tutorial...

Page 32: ...cked by the system clock They are 32 bit count down timers they have to be initialised with a start value Reaching 0 and restarting triggers an interrupt Enhanced Modular I O Subsystem eMIOS This modu...

Page 33: ...NT The counter goes up to 0xFFFFFFFF and then starts again from 0x00000000 Each of the four channels 0 3 have the following registers STM Channel Control Register STM_CCR n with a one bit enable field...

Page 34: ...DVAL with a 32 bit TSV Timer Start Value field Current Timer Value Register CVAL with a 32 bit TVL Timer Value field Timer Flag Register TFLG with a one bit timer interrupt flag field TIF write 1 to c...

Page 35: ...can trigger a wakeup or interrupt event The Autonomous Periodic Interrupt API module can trigger wakeup or interrupt events periodically a 10 bit period value is added to the bits 22 31 of current val...

Page 36: ...bling 512 32 divider these dividers allow to get counter period slow enough to measure important amounts of time these dividers should be set before enabling the counter APIVAL API Compare Value this...

Page 37: ...o roll over after a match The 8 bit prescaler field is not large enough to make a 5Hz roll over therefore after each match interrupt the counter has to be reset This will deteriorate the resulting fre...

Page 38: ...ules use timer channels to generate or measure time based events like PWM counter generation period measurement etc Channels can be configured up to 12 different operation modes shown on the figure be...

Page 39: ...mode when set a Freeze FRZ bit to freeze each channel in debug mode which would allow better debugging Global Time Base Enable GTBE bit is for enabling the global 8 bit counter of the eMIOS module Glo...

Page 40: ...01 or the eMIOS internal counter 11 This clock has to be enabled using Prescaler Enable UCPREN bit and it can be prescaled using UCPRE clock divided by UCPRE 1 Direct Memory Access DMA bit selects if...

Page 41: ...e 1 to clear which is set when a flag generation occurs while FLAG was already set Overflow bit OVFL write 1 to clear is set when an overflow has occurred in the internal counter Two read only fields...

Page 42: ...pture output compare and timing functions are disabled Registers A and B hold the same value All channels are in this mode by default and have to go through this mode when a mode change occurs Counter...

Page 43: ...e flag bit is set and the value of the selected counter bus is captured by A2 and can be read through the register A Figure 49 SAIC with rising edge triggering example R M Rev8 Fig 24 18 1 4 SAOC Sing...

Page 44: ...read on the register B By subtracting B1 from A2 we can get the pulse width See figure below for an illustration of these register transfers Therefore once a flag is set reading the register A then re...

Page 45: ...pare In the Double Action Output Compare mode a variable output pulse is generated by matches occurring on comparators A and B At initialisation the output flip flop is set to the complement of the ED...

Page 46: ...if it is clear then the internal prescaled clock source is used MODE 5 defines whether the internal counter is cleared on match start or on an match end When this bit is clear the counter is cleared...

Page 47: ...ure 55 MCB Up Counter Mode Example R M Rev8 Fig 24 32 The configurable bits MODE 4 and MODE 6 have the exact same effect as on the MC mode When the counter is in up mode the period will take A1 cycles...

Page 48: ...ange after edge detection has an intrinsic one system clock cycle delay The example on the figure above shows that this causes an important effect when the internal counter frequency is close to syste...

Page 49: ...e a up down MCB counter It is also recommended to start the MCB channel after starting the OPWMCB mode Figure 59 OPWMCB with lead dead time R M Rev8 Fig 24 41 Register A1 controls the duty cycle for t...

Page 50: ...M if it is set a flag will be generated on both edges The MODE 6 bit is for selecting between leading edge 1 or trailing edge 0 dead time insertion 1 12 OPWMB Output Pulse Width Modulation Buffered Th...

Page 51: ...fixed period PWM with a fixed leading edge precisely positioned in reference to a time base which is a counter in MC up starting from 0 or MCB up starting from 1 mode a variable trailing edge controll...

Page 52: ...base bus using BSL 12 PWM channel Select the specific PWM mode 13 PWM channel Set prescaler ratio 14 PWM channel Enable channel prescaler 15 eMIOS Enable global prescaler 4 PWM Example For a simple e...

Page 53: ...we can select channel 21 set the leading edge register A at 0 and trailing edge at 499 running on bus A with a positive polarity output is set at leading edge etc This gives us a PWM at 1kHz with 50 d...

Page 54: ...t conversion modes like one shot or scan There is also a chain injection possibility Each channel has individual conversion registers There are three types of input channels 16 internal precision ADC0...

Page 55: ...e is done Figure 65 Normal conversion flow of channels B C D and E R M Rev8 Fig 25 2 In scan mode the sequential conversion of these channels is continuously executed NSTART bit is automatically set o...

Page 56: ...nfigured and each type of channel type can have a particular timing setting Conversion time consists of a sampling phase a latching phase and an evaluation phase Figure 67 Sampling and conversion timi...

Page 57: ...guarded area limited by a lower and an upper threshold Figure 70 Analog Watchdog R M Rev8 Fig 25 7 Table 25 5 In the watchdog status register two bits called WDGxH and WDGxL whether there has been a t...

Page 58: ...cleared one shot mode is selected else scan mode is selected Normal Start conversion NSTART starts a normal mode conversion when set see sections above Injection external trigger enable JTRGEN Inject...

Page 59: ...code signals and the sampling phase It is useful for taking in account the settling time of the external multiplexers It has a 8 bit field called DSD and it introduces DSD 2 ADC clock delays The Power...

Page 60: ...the flag bits of the interrupts generated by the ADC peripheral There are five flag bits that are set when an interrupt is raised and they have to be cleared by writing 1 these are EOCTU End of CTU co...

Page 61: ...r standard channels and 64 95 are for external multiplexed channels These registers contain information about the converted result The field VALID notifies if a new value has been written and it is au...

Page 62: ...rom the SIUL LEDs have to be selected as GPIO output two buttons as GPIO inputs two pins as eMIOS channels and a pin for ADC input eMIOS is initialised with a prescaler of 8 for getting 1MHz internal...

Page 63: ...time out of 8000 and ADC s end of conversion interrupt is connected to the ADC_EOC_Interrupt handler Depending on an internal state variable the value read by the ADC either affects the OPWM s duty cy...

Page 64: ...r which makes a connection between the trigger source and an ADC channel to be converted A FLAG_ACK signal is sent to the event source if the source is a PIT for eMIOS the flags are cleared automatica...

Page 65: ...Figure 76 Trigger Sources R M Rev8 Table 26 3 2 Configuring CTU Figure 77 Event Configuration Registers R M Rev8 Fig 26 2...

Page 66: ...a CTU conversion is triggered while a normal conversion is ongoing it is treated just like an injected conversion The normal conversion is aborted and it resumes once the CTU conversion is completed...

Page 67: ...the ADC initialisation where the CTU triggers are enabled And the eMIOS channel is changed to an OPWMT from generating triggers with alt A register And in the main code the CTU is set so that eMIOS c...

Page 68: ...can run on all clocks except the FMPLL The system clock is by default on FIRC clock but it can be disabled Data and Code flash memories are by default powered down but can be activated and the main v...

Page 69: ...RC and SXOSC This mode is usually configured to run on SIRC or FIRC running on SIRC and disabling FIRC saves even more power When a wakeup signal is received the device modes and clock are reconfigure...

Page 70: ...located on some specifics pads of some ports that has also communication functionalities like CAN or LIN This can allow for example to put the device en low power mode while awaiting information comm...

Page 71: ...unit has a few registers for configuring and managing wakeup events all of them have a 20 bit modifiable field with each bit being associated to a wakeup source The Wakeup Interrupt Filter Enable Reg...

Page 72: ...OUT in DSPI Slave Master Input Slave Output data sent by the slave SS or CS in DSPI Slave Select Chip Select selection of a slave In MOSI MISO naming convention MOSI of the master is connected to MOSI...

Page 73: ...case where the master has only one chip select signal then a configuration called daisy chained SPI can be used In this chain each device sends its data to the next device and receives from the previo...

Page 74: ...mory for simpler communication various interrupts and a precise control on the baud rate and delays Figure 87 The DSPI module block diagram R M Rev8 Fig 23 1 Each DSPI module has six chip select CSx s...

Page 75: ...e DSPI transfers halt at the next frame boundary MTFE Modified timing format enable see below for more details PCSSE Peripheral Chip Select Strobe Enable when enabled CS5 signal can be used on an demu...

Page 76: ...Modified transfer format On classical SPI transfer formats CPOL and CPHA are enough to define the clock polarity and which edges to use for capturing or changing the data The modified transfer format...

Page 77: ...ormat R M Rev8 Fig 23 16 2 3 1 Data attributes These attributes are used to select the parameters related to the transferred data like its size its order on which edge it is read or changed FMSZ frame...

Page 78: ...r value is either 2 00 3 01 5 10 or 7 11 Master mode only DBR double baud rate doubles the SCK baud rate but depending on PBR and CPHA it might alter the 50 50 duty cycle of the clock see at right Mas...

Page 79: ...after the SCK stop the delay scaler value is 2 0 3 1 Master mode only 2 3 5 After transfer delay These fields are used to set the minimum CS idle time between two transfers This delay is not used in...

Page 80: ...ive FIFO drain flag indicated that there are data in RXFIFO that can be read TXCTR RXCTR indicates the number of entries in the TX RX FIFO TXTNXTPTR Transmit next pointer indicates which TX FIFO entry...

Page 81: ...f duplex modes has been developed in C language A structure was used to represent a DSPI module s driver with function pointers in it for better user interface Transfer methods implemented in this dri...

Page 82: ...achine has been implemented for executing different handlers depending on the transfer method that is used The user is free to add their own states for their own handling needs and modify other method...

Page 83: ...tus The outputs are high side switches N MOSFETs with an RDSon of 4mOhms In this example we will develop a serial terminal interface for MPC5604B for commanding this chip It will have to initialise th...

Page 84: ..._INx field is therefore used for enabling a switch The FS pin can be used to trigger interrupts on falling edges via External Interrupt registers in SIUL This will allow getting an instant fault treat...

Page 85: ...The initialization function of the driver sends required RST and WAKE signals to prepare the device and it configures some basic parameters using SPI This function also calls eMIOS initialisation fun...

Page 86: ...ng Most of this driver s functionalities were tested Firstly Freescale s SPIGen program was used with an SPI Dongle to test read and write actions on the device s registers Then the developed terminal...

Page 87: ......

Page 88: ...Stop Bits like 9600 8N1 which means 9600 kbit s 8 data bit no parity bit and one stop bit very common configuration N is for no parity E is for even parity and O is for odd parity Up to 3 of baud rate...

Page 89: ...8 Fig 21 3 There are three operating modes as shown on the figure above the sleep mode is the low power state normal mode is the state where a communication is possible and the initialization mode is...

Page 90: ...Register UARTCR allows configuring different parameters related to this protocol Different fields of this register are UART UART mode enable set this bit to be able to modify other fields of this reg...

Page 91: ...IV_F field where DIV_F 16 _ LFDIV There will be some error in baud rate values and an error over 1 1 5 should be avoided if the system clocks are imprecise Figure 101 Error calculation for programmed...

Page 92: ...Flag when set there is a parity error in the received byte x in the buffer OCF Output Compare Flag this flag is related to the LINFlex module internal counter Not explained here SZF Stuck at Zero Fla...

Page 93: ...ng function called rprintf for sending simple messages that might contain information about internal data Example struct _UART_DRV UART UART variable has to be imported from the UART Driver module uin...

Page 94: ...ovides a simple command line interface for reading data from ADC and driving output PWM Using commands like ADC get x for getting data from ADC channel x PWM start for launching a PWM PWM stop for sto...

Page 95: ...rsion will be made on a user request As the system clock is 64MHz we will set ADC to the maximum possible clock 32MHz with the minimum timing parameters given in the documentation Only channel 0 conne...

Page 96: ...modulus counter giving a 1kHz roll over frequency And the channel 22 is configured as OPWMB with a 50 duty cycle initially A function for setting the duty cycle is implemented 5 5 Main procedure and u...

Page 97: ...cation with a PC The program waits for an ASCII message made of 3 strings separated by space characters ending with a NUL character The first string is 10 bits long and stored in 0 9 addresses of RxBu...

Page 98: ...mple works as foreseen basic commands are executed through a friendly user interface One may even create a GUI exploiting COM port drivers to communicate with the device Error management is really imp...

Page 99: ...You can see a communication example below where unknown commands are dismissed and other ones correctly executed...

Page 100: ...can initiate a communication with a slave either for transmitting or receiving and most of the devices can switch between master and slave modes These communications start with a start signal which i...

Page 101: ...figure below you can see a communication example where the master transmits a command to the slave and then it proceeds to receive data from it The master uses NACK signal to stop the communication Th...

Page 102: ...ing 50 100pF m on cables 1 3 Pull up resistor calculation Pull up resistance value is limited by low level current consumption of the devices and the RC time constant of the bus cause by the bus capac...

Page 103: ...ule control two for status management and two others for address and data Frequency setting The baud rate of this module can be configured using the I C Bus Frequency Divider Register IBFD who has an...

Page 104: ...loses arbitration o TXRX Transmit Receive mode select 1 for transmit When operating as a slave this bit should be set according to the demands of the master and when operating as a master it is used d...

Page 105: ...set according to this request RXAK Received Acknowledge this bit is set when no ACK signal is received IBIF I Bus Interrupt Flag this flag is set on the following conditions IBAL is set TCF is set IA...

Page 106: ...in to the data register IBDR Wait for IBB flag to be set start signal and slave address are sent During a transfer use the interrupt handler to check status register and take action depending on mast...

Page 107: ...a typical I C interrupt handler R M Rev8 Fig 20 13 2 4 Developing a general purpose I C Driver A driver can be built for this module similar to the one for DSPI or UART building methods around the pr...

Page 108: ...deterministic multiple devices can try to transmit at the same time only one of them will prevail and the others wait for the bus to become idle CAN controllers possess multiple error detection metho...

Page 109: ...Command field has two reserved bits for future standards one of them is used in CAN 2 0B to specify an extended ID or not at dominant state and a 4 bit DLC Data Length Code field which indicates the n...

Page 110: ...l medium with differential voltages Figure 113 A typical CAN transceiver and CANH CANL signals In high speed CAN standard CANH and CANL are derived from TX to from a differential voltage with two stat...

Page 111: ...e this error occurs But the error is not raised during arbitration or acknowledge fields because it is expected to have different values for these phases Stuff error CAN bus specifies that over 6 bits...

Page 112: ...hronization jump width These methods are illustrated on the following figure Figure 116 Bit time resynchronisation methods Propagation segment Takes in account the delay due to the propagation speed o...

Page 113: ...ndition min 20 bit_time min Phase_seg_1 Phase_seg_2 2 13 bit_time Phase_seg_2 A simpler but less sure method is to pick a bit time with 12 to 20 usually 16 and assume that sampling point is at the 75...

Page 114: ...e registers that are mapped to the memory of the microcontroller in FlexCAN s case there is an embedded SRAM and it can be configured either as 64 16 byte Message Buffers MB with an intelligent MB man...

Page 115: ...r a read if a new frame is received then the state will remain the same If a new frame is received before the buffer is read the next state will be RX OVERRUN RX OVERRUN 0110 an unread full buffer was...

Page 116: ...t is assumed that user wants to read the whole MB so its contents are locked and cannot be altered until the user makes a dummy read of the free running timer TIMER register or until it reads another...

Page 117: ...eria over the 8 most significant bits of the ID D All frames rejected Figure 122 Fields of the ID Table words depending on the selected ID mode R M Rev8 Fig 22 4 The figure above shows the different f...

Page 118: ...on reception BCC Selection between legacy masks 0 and individual masks 1 for ID filtering see below LPRIO_EN enables local priority for Tx MB arbitration by adding 3 more address bits not transmitted...

Page 119: ...message is received in MB0 or MB8 if FIFO enabled This messages synchronises internal counters therefore the increasing the value of the timestamp LOM Listen Only mode when set FlexCAN will freeze all...

Page 120: ...is set when FlexCAN goes into Bus Off state depending on counters An interrupt is generated if the mask in CTRL is set Write 1 to clear ERR_INT Error interrupt if at least one of the x_ERR bits is se...

Page 121: ...configuring the transceiver see section 4 and configuring the module and its buffers It also configures a timer to raise an interrupt every 200ms Then the main loop implements a state machine with tw...

Page 122: ...cleared set their control and status words 4 Initialise ID filtering register Individual Mask registers or the global mask registers depending on MCR 5 Configure interrupts and their masks 6 Negate th...

Page 123: ...ion or a simple flag And then it can be read by first accessing the Control and Status word for activating the internal lock then reading the ID and the Data and then making a dummy read on the Free R...

Page 124: ...suggests powering up the board from USB and letting the external power supply only work on the SBC For putting SBC to the debug mode a voltage over 8V must be applied to the DGB TP1 pin This can be do...

Page 125: ...in sleep mode wake up disabled 0x6080 set CAN in sleep mode wake up enabled 0x6040 set CAN in receive only 0x60D8 set CAN in TxRX mode medium slew rate The advantage of using the debug mode is avoidin...

Page 126: ...basic library for resetting the device setting software INTC mapping registers to the memory etc For creating a new project first you have to select your device Then you can select your project s name...

Page 127: ...he header files click right and add file Let s open and see what we can do with a complete project like the SPI Driver self test program For building a project you should use Compile Make and Debug in...

Page 128: ...ariables where you should have While programming you will need a lot of peeking into the MPC5604B_0M27V_102 h file because it contains registers mapping For instance the ADC MCR register is defined by...

Page 129: ...tion to only modify it but if the optimisation level is too high unpredicted behaviour might occur with these fields At the end of the mapping file a volatile variable based on each peripheral structu...

Page 130: ...debugger you ll have to click Connect Reset It will start by initialising the debugger and the download the code and data to the flash Debugger while the flash is being programmed Once the debugger is...

Page 131: ...The variable windows at left allow you to add variables from the program even arrays and structure and monitor them You can also add peripheral registers using add register You can also monitor the me...

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Page 133: ...127 Appendix 2 Pad Configurations...

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Page 141: ...Appendix 3 Peripheral input pin selection...

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Page 143: ...137 Appendix 4 Interrupt Vector Table...

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