Freescale Semiconductor MPC5604B, Quick Start Manual

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The led will blink with a frequency of 1Hz. It should be noted that it’s common to use finite state
machines in interrupt handlers.
2.3. Configuring software ISRs
There are 8 ISRs that can be triggered by the software, the ISR configuration is done in the same
way as hardware ISRs but triggering the interrupt is more complicated. On hardware ISRs,
peripherals are in charge for triggering the interrupt (a button is pushed, a timer has reached a
limit value, an ADC conversion is done etc.)
Figure 32 : INTC Software Set/Clear Interrupt Register (R.M. Rev8 – Fig. 16-7/8)
For triggering a software interrupt we use INTC Software Set/Clear Interrupt Registers SSCIR,
each one of these 8-bit registers can trigger a software ISR (writing ‘1’ to SET) and can clear the
flag by writing ‘1’ to CLR.
2.4. Enabling nested interruptions
By default nested interruptions are not enabled, the prologue of INTC handler does not save
every register, this causes a loss of time in interrupt priority handling when a higher priority
interrupt is triggered while a lower priority is being processed. When nested interrupts are
enabled, a higher priority interrupt can pause the handler of a lower priority and finish it up
later (which can sometimes lead to unexpected results in the paused handlers). When nested
interrupts are disabled, higher priority handling has to wait the end of the previous one.
To enable nested interruptions, the user needs to change the value of
INTC_NESTED_INTERRUPT macro at line 17 of “IntcInterrupts.c” to 1.
3. Hardware mode INTC
Previously explained ISR method is only used in software interrupt mode of INTC where the
prologue and epilogue is common to all interrupt. In applications where avoiding saving some
registers is affordable and needed for saving time, it is possible to use hardware interrupts
where the prologue and epilogue are customisable.
The following figure shows the functionality difference between HW and SW mode, if you need
to use HW mode interrupts, then you’ll need to add appropriate handler branch instructions to
the intc_hw_branch_table_vle.s as explained on the figure (see cookbook example) and define
handlers with prologue & epilogue on a handlers_vle.s.