Freescale Semiconductor MPC5604B, Quick Start Manual

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Chapter 9
DSPI: Deserial Serial Peripheral Interface
1. Introduction
There are three identical DSPI modules (0…2) in this microcontroller for using SPI serial bus
protocol in order to communicate with external devices.
1.1. SPI Protocol Description
The Serial Peripheral Interface (SPI) is a synchronous serial communication bus in which there
is only one master and at least one slave. This bus can operate in full-duplex mode, transmitting
and receiving at the same time. There are at least four logical signals but in a single slave
situation only three of them can be enough.
Figure 84 : SPI Master/Slave Illustrations
These signals are:

SCLK (or SCK in DSPI): a clock generated by the master to synchronise the exchange,

MOSI (or SOUT in DSPI Master, SIN in DSPI Slave): Master Output Slave Input, data sent
by the master

MISO(or SIN in DSPI Master, SOUT in DSPI Slave): Master Input Slave Output, data sent
by the slave
 SS (or CS in DSPI): Slave Select (Chip Select), selection of a slave.
In MOSI/MISO naming convention, MOSI of the master is connected to MOSI of the slave and
similarly their MISO are connected together, but in SOUT/SIN naming convention (DSPI’s case),
SOUT is connected to SIN and SIN to SOUT.
There is a shift register in both master and slave (usually 8-bit) and following the clock ticking of
the master, these registers are rotated until the data in them is completely exchanged.
There are many parameters about details of this transmission that can be configured, and both
master and slave has to have similar configurations for valid communication like the frame size
(shift register’s size). The master’s clock frequency is also called the SPI Baud Rate, image of the
data transmission speed, can be selected on a wide range on values, and this clock’s polarity
(CPOL) can be selected. Another important parameter is the clock phase (CPHA) with defines
the edge where the data is sampled.