Freescale Semiconductor MPC5604B, Quick Start Manual

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2. Channel Configuration
1.1. Introduction
Unified Channels are made of:
- A counter bus selector, which can select among three time base sources, to be used for time-
based events.
- An internal 16-bit counter clocked by the prescaled eMIOS internal clock.
- Two data registers A and B, double buffered and related to four internal registers (A1, B1,
A2, and B2) that can be used for input capture or output compare.
- Programmable input filter.
- Programmable edge detector.
- An output flip-flop for buffering the logic levels.
Each channel has a control register (EMIOS_CH[n]_CCR) defined as:
Figure 45 : eMIOS Channel Control Register (R.M. Rev8 – Fig. 24-15)

Freeze Enable (FREN) bit allows freezing all channel register values in debug if eMIOS
block’s FRZ bit is set.

Bus Select field (BSL) allows to choose between counter bus A (00), secondary counter bus
(B, C, D or E) (01) or the eMIOS internal counter (11). This clock has to be enabled using
Prescaler Enable (UCPREN) bit and it can be prescaled using UCPRE (clock divided by
UCPRE+1).

Direct Memory Access (DMA) bit selects if the FLAG generation leads to an IRQ (0) or a CTU
trigger (1). (See CTU chapter). To enable flags, FEN bit has to be set.

Input Filter (IF) selects the minimum input pulse width that can pass through the filter
(0000: bypassed, 0001: 2 FLT_CLK periods, 0010: 4 periods, 0100: 8 periods, 1000: 16
periods). The Filter Clock (FCK) can either be the main clock (1) or the prescaled clock (0).

While using an output mode, Force Match A/B bit (FORCMA/B) generates a successful
comparison with register A/B. Can be used to force the output to a value.

Edge Polarity (EDPOL) bit: for input modes selects whether a rising (1) edge or a falling (0)
edge triggers and event (a counter, capture or a flag). For output modes, this bit selects the
logic level on the output pint: if it’s set to ‘1’, a match on A sets the output while a match on
B clears it. (It’s the opposite if it’s set to ‘0’).