Freescale Semiconductor MPC5604B, Quick Start Manual

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When in GPIO input mode (MODE[0:6]=0000000), the input pin status can be read by UCIN bit
in the status register and a flag can be generated at on a rising or an falling edge. (Detection of
both edges isn’t implemented for GPIO).
In GPIO output mode (MODE[0:6]=0000001), the channel is used as a single output pin and the
value of EDPOL is transferred to the output flip-flop.
1.3. SAIC: Single Action Input Capture
This is the Single Action Input Capture mode (MODE[0:6]=0000010), when a triggering event
on the input (a rising, falling or either edges) occurs, the flag bit is set and the value of the
selected counter bus is captured by A2 and can be read through the register A.
Figure 49 : SAIC with rising edge triggering example (R.M. Rev8 – Fig. 24-18)
1.4. SAOC: Single Action Output Compare
This is the Single Action Output Compare mode (MODE[0:6]=0000011), a match value written
in the register A is written to A2 and transferred to A1 directly where it’s compared with the
selected time base (the BSL field of the control register). When a match occurs, the flag bit is set
and depending on EDSEL, either the output flip-flop is toggled or the value in EDPOL is
transferred to it.
At initialisation, the flip flop is set to the complement of EDPOL.
Figure 50 : SAOC with both possibilities on EDSEL (R.M. Rev8 – Fig. 24-20/21)