In Layer 2 mode, once the time axis is established (whether passive or active), the chip will
continue to give the TIME_SLOT_INTER and Rdy_lst_inter shown in the figure above for 30ms.
Rdy_lst_inter is not a separate interrupt pin. The terminal multiplexes an interrupt pin output with
Sys_inter. The multiplexing mode is the same as the three-layer interrupt usage description in 5.1.1.
The t1 time is the start time of the code sending framing frame, t2 is the software preparation data
and the configuration transceiver control command time, and t3 is the time from the end of the time
slot to the Sys_inter interrupt to the CPU.
The chip is in position 1 or position 2, giving TIME_SLOT_INTER or Rdy_lst_Inter. The CPU can
set the time slot 2 to be transmitted or received according to one of the two interrupts (0x41, Bit7,
Bit6).
If time slot 1 is received, then at position 4 the CPU can read the data received in that time slot and
provide a decision basis for the next action of the CPU.
Assuming that time slot 1 is received, and time slot 2 is set to transmit after the position 1
(TIME_SLOT_INTER interrupt) and before position 2 (Rdy_lst_inter interrupt), the chip will give
RF_TX_INTER for the CPU to set the RF channel correlation. parameter.
Assuming that time slot 1 is a transmission, and time slot 2 is set to receive after the position 1
(TIME_SLOT_INTER interrupt) and before position 2 (Rdy_lst_inter interrupt), the chip will give
RF_RX_INTER for the CPU to set the RF channel correlation. parameter.
According to the active-passive mode established by the time axis, the transmission and reception
mode control of the time slot of the whole machine is combined into a working mode:
1) Active sending
Active sending means that the system is currently in an out-of-synchronization state, initiates a call,
and generates synchronization information locally. This situation is mainly applied to the
HR_C6000 initiative to initiate single and duplex transmission.
MCU setting send register 0x40 turn on active send 0xA3;
The establishment of this flag bit will cause the chip to generate active transmission synchronization
information, and send a 30ms interval interrupt to the MCU through TIME_SLOT_INTER;
After receiving the 30ms interrupt, the MCU reads the 0x42 status bit7-5 and judges the current
time slot transmission and reception:
001 indicates that the current time slot is a working time slot, but the transceiver is fully closed;
101 indicates that the current time slot is a working time slot, and the sending is enabled;
011 indicates that the current time slot is a working time slot, and reception is enabled.
xx0 indicates that the current time slot is a non-working time slot, and the transceiver does not need
to be opened;
The MCU obtains the time slot transmission and reception status of the HR_C6000 to determine the
operation requirement of the next time slot according to the protocol.
