waiting
transmission
preparation
interrupt
Idle
Send
configuratio
n
preparation
Enable the
next time
slot
transmission
enable
Figure 5.10 Flow chart of the Layer 2 sending process
5.4.4 Working mode description
Working in Layer 2 mode, the synchronization time axis of the 30ms time slot required in the whole
machine is provided by HR_C6000, while the HR_C6000 provides 30ms time axis. There are two
modes, one is generated by HR_C6000 own clock, which provides 30ms stably. Interrupt, called
active mode, the other is that the 30ms interrupt provided by HR_C6000 will continuously adjust its
30ms (approximate) interrupt output according to the signal received by HR_C6000 (including the
sync head signal), which is called passive mode.
Active mode: CPU setting HR_C6000 Active mode (Register reg0x40 Bit5 is configured to 1, 1 of
Bit6 and Bit7 must be 1), establish a time slot, and provide 30ms interrupt to the MCU.
Passive mode: CPU setting HR_C6000 register reg0x40 Bit5 is configured as 0 (where Bit6 and
Bit7 must have one). HR_C6000 enters the receiving state. The system starts to establish
synchronization according to the synchronization information of the received signal, and continues
to receive synchronization information according to the received information. To adjust the
synchronization timeline to provide a 30ms (approximate) interrupt to the MCU.
After the complete time axis is established, the chip has the conditions for sending and receiving.
On this basis, the chip will provide the CPU time slot interrupt Time_slot_inter, which is used to
inform the CPU of the middle position of the time slot of the entire time axis. The CPU plans the
corresponding according to the time axis. Receive, send, and perform correct control and data
transmission.
Bit 7 of Register 0x40 is the transmission, and Bit6 is the reception. This is the control signal that
the CPU tells the chip to transmit or receive. Only when one of the two signals is valid, the time
axis will be established, but these two signals will not be independently controlled. The
transmission and reception of time slots is enabled, and the control of time slot transmission and
reception is Bit 7 (send) and Bit 6 (receive) in register 0x41.
Figure 5.11 Schematic diagram of Layer 2 interrupt distribution
