4
Application note
4.1 Chip reset
4.1.1 Power-on reset
The HR_C6000 can be powered on and reset using resistors and capacitors. The reference circuit is
as follows.
OMISSIS
Figure 4.1 Chip Power-on Reset Reference Circuit
To ensure a successful power-on reset, the reset time is required to be kept to a minimum of 0.1μs. s.
As shown, 0-0.8V is stable low power flat voltage range, 2.0-3.3V is a stable high-level voltage
range.
OMISSIS
Figure 4.2 Chip power-on reset timing diagram
It is recommended to use the same reset chip as the CPU or the GPIO of the CPU as the reset pin.
4.1.2 Software reset
In addition to the automatic reset process during power-on, the HR_C6000 can also pass the MCU
according to the actual application needs.
Software reset the chip. The software reset operation is implemented by Bit7 of the configuration
register Reg0x00. Will be Reg0x00
After Bit7 is configured as 0, a soft reset of HR_C6000 is completed, and the reset time is a
Sys_Clk pulse width, that is, 1/9.8304 uS. After this bit is configured as 0, it is not necessary to
reconfigure to 1 to resume normal operation mode through the MCU. The HR_C6000 automatically
sets Bit to 1.
OMISSIS
Figure 4.3 Chip Software Reset Timing Diagram
4.2 Chip power supply
The HR_C6000 requires 3.3V power supply and the built-in DCDC module outputs 1.2V for digital
and analog cores. By outside The circuit separates the analog 3.3V, digital 3.3V and analog 1.2V,
digital 1.2V power supplies. Digital 1.2V and digital 3.3V
The power supply shares digital ground; all analog 3.3V common ground; all analog 1.2V common
ground.
The power supply network is shown in the figure, where VCC33 provides the total power supply
for the system and AVDD33 is the chip to simulate the 3.3V power supply.
