The DVDD33 is a chip digital 3.3V power supply. AVDD33 provides on-chip DCDC module for
conversion of output chip 1.2V analog power supply AVDD12 and digital power supply DVDD12.
OMISSIS
Figure 4.4 HR_C6000 power reference circuit
4.3 Chip working clock block diagram and description
4.3.1 Clock circuit
The HR_C6000 requires an optimum bias of 1.5V for the crystal. At this bias, the crystal output
requires Vpp ≥ 2V. Chip The clock is input by the XTALI pin.
OMISSIS
Figure 4.5 HR_C6000 clock reference circuit
4.3.2 Clock configuration
Configure the relevant registers of the built-in PLL of the chip, so that the input clock is locked to
CLK via PLL (recommended value is 49.152MHz), and the internal frequency of the chip is
Sys_clk, Clk_codec, CLKOUT. The Sys_clk is the system working clock. Configuration register
0xB9 is obtained, Sys_clk is 9.8304MHz; Clk_codec is the built-in Codec working clock, which is
configured by register 0xBA and has a frequency of 12.288MHz. CLKOUT can provide working
clock for external Codec or vocoder. The clock frequency can pass 0xBB register. Configure and
additionally configure bit 0 (ClkOut_enb) of Register 0x0A to control whether to output the
CLKOUT clock and output a valid clock when high.
When the HR_C6000 is powered on, the internal working clock is directly provided by the external
crystal oscillator by default, that is, bit7 of 0x0A is 1. After changing the configuration reg0x0B and
reg0x0C, it needs to wait for more than 500μs. s. Wait for the PLL output to be stable enough before
switching the internal clock back from the crystal oscillator. PLL output.
OMISSIS
Figure 4.6 Chip Operating Clock Block Diagram
The built-in PLL of the chip is configured through the 0x0B, 0x0C registers. The specific
calculation formula is as follows:
CLK=XTALI×PLLM / PLLN / NO;
