ERM HR C6000 User Manual Download Page 6 | Manualshive

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2.1 Pin map

OMISSIS

HR_C6000 pin diagram picture is missing

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Summary of Contents for HR C6000

Page 1: ...ATOR TAKES NO RESPONSIBILITY FOR ANY INACCURACY OF THIS DOCUMENT AND FOR ANY DAMAGE FOLLOWING AN INAPPROPRIATE USE OF THE DEVICES AND NOT FOLLOWING THE ORIGINAL MANUFACTURER INSTRUCTIONS IF YOU DON T UNDERSTAND SOMETHING LOOK AT THE ORIGINAL DOCUMENT AND ASK SOMEONE TO TRANSLATE IT FOR YOU This version 0 2 ...

Page 2: ... and other vocoders automatically by HR_C6000 Complete the configuration of the vocoder and control the data exchanged with the vocoder Support for digital voice encryption RF interface Transmit RF interface with single ended output support baseband IQ intermediate frequency two point modulation Receive RF interface with differential input supporting baseband IQ IF and AF Send two signal offsets t...

Page 3: ...orten the development time users can also perform PDT based on the HR_C6000 Layer 2 protocol Development of protocols DMR TierIII or custom protocols to meet the needs of high end users The chip is suitable for digital intercoms dedicated cluster terminals as well as low speed data and voice transmission terminal applications support relay and terminal applications in a centralized mode The chip h...

Page 4: ...iguration interface 14 4 5Use of Codec 17 4 5 1Built in Codec 17 4 5 2Use external Codec 17 4 6Vocoder 18 4 6 1Interface definition with Hongrui HR_V3000 vocoder 18 4 7Transmitter module 20 4 7 1Baseband IQ modulation 21 4 7 2Two point modulation 21 4 7 3IF IQ modulation 21 4 7 4IF modulation 21 4 8Receiving module 21 4 8 1Baseband IQ 21 4 8 2IF mode 21 5Hierarchical function description 21 5 1Int...

Page 5: ...1 Chip block diagram OMISSIS ...

Page 6: ...2 Chip pin 2 1 Pin map OMISSIS HR_C6000 pin diagram picture is missing ...

Page 7: ...3 PLL_VSS33 AG The PLL simulates ground 14 XTALI DI System clock active crystal input 15 CLKOUT DO HR_C6000 output clock when output by PLL clock divider is obtained the division ratio is matched by reg0xBB Set Available for external Codec or external vocoder use External Codec interface working clock which is clocked by CLKOUT is provided if the external Codec is not used CLKOUT the clock needs t...

Page 8: ...utput data signal 26 McBSP_CLKX DI AMBE3000 McBSP connection of HR_C6000 Port input clock 27 McBSP_FSR CHS_I_STRB DO AMBE3000 HR_C6000 by McBSP The data synchronization letter sent by the interface to the AMBE3000 number AMBE1000 CHS_DI port data is valid Enable 28 PKT_RX_WAKE CHS_O_STRB DO AMBE3000 Invert McBSP_FSR Used to wake up the McBSP interface AMBE1000 CHS_DO port data is valid Enablement ...

Page 9: ...is provided from the mode the vocoder HR_C6000 reads and writes the left and right channels of serial data Enable 38 TEST_MODE DI Test mode configuration pin 1 is test mode 0 for normal working mode 39 RESETn DI System reset signal active low 40 VSS33 P Digital IO 3 3V power supply 41 V_SDI DI Universal vocoder SPI port serial data input 42 V_SDO DO Universal vocoder SPI port serial data output 43...

Page 10: ...AI Q The negative side of the ADC channel differential input 63 ADC_QVINP AI Q Positive side of the ADC channel differential input 64 ADC_AVDD12_Q AP The Q channel ADC channel simulates a 1 2V power supply 65 ADC_AGND_Q AG Q channel ADC channel analog ground 66 ADC_AVDD33_Q AP ADC Analog 3 3V Power Supply 67 ADC_AVDD33_I AP ADC Analog 3 3V Power Supply 68 ADC_AGND_I AG I channel ADC channel analog...

Page 11: ...power supply 77 DCDC_VDD12 AO DC DC 1 2V output 78 DCDC_VSS G DC DC digital ground 79 DCDC_VDD33 P DC DC 3 3V power supply 80 DCDC_SW O DC DC internal switch 2 3 Package size OMISSIS 3 Chip characteristic 3 1 Static characteristic Table 3 1 HR_C6000 Static Parameters OMISSIS 3 2 Dynamic characteristics OMISSIS 3 3 Power consumption parameter OMISSIS 3 4 Performance parameter OMISSIS ...

Page 12: ...et operation is implemented by Bit7 of the configuration register Reg0x00 Will be Reg0x00 After Bit7 is configured as 0 a soft reset of HR_C6000 is completed and the reset time is a Sys_Clk pulse width that is 1 9 8304 uS After this bit is configured as 0 it is not necessary to reconfigure to 1 to resume normal operation mode through the MCU The HR_C6000 automatically sets Bit to 1 OMISSIS Figure ...

Page 13: ...ation register 0xB9 is obtained Sys_clk is 9 8304MHz Clk_codec is the built in Codec working clock which is configured by register 0xBA and has a frequency of 12 288MHz CLKOUT can provide working clock for external Codec or vocoder The clock frequency can pass 0xBB register Configure and additionally configure bit 0 ClkOut_enb of Register 0x0A to control whether to output the CLKOUT clock and outp...

Page 14: ...parameters PLL output clock System clock configuration parameter System output clock 12 288M Reg0x0B 0x40 Reg0x0C 0x32 49 152M Reg0xB9 0x05 Reg0xBA 0x04 Reg0xBB 0x02 Sys_clk 9 8304 Clk_codec 12 288M CLKOUT 24 576M 29 4912M Reg0x0B 0x28 Reg0x0C 0x33 49 152M Reg0xB9 0x05 Reg0xBA 0x04 Reg0xBB 0x02 Sys_clk 9 8304 Clk_codec 12 288M CLKOUT 24 576M 4 4 Chip parameter configuration interface The MCU uses ...

Page 15: ...terface timing is shown in the figure below OMISSIS Figure 4 8 U_SPI Interface Read and Write Timing SCLK supports up to 4MHz clock rate The MCU can control the Sleep state of the HR_C6000 through the GPIO pin When the GPIO is pulled high the chip is in the Sleep state and all clocks in the HR_C6000 are turned off ...

Page 16: ...s HR_C6000 provides 4 interrupt pins the interrupt low pulse is valid the pulse width is 3 system working clocks Sys_clk 9 8304MHz SYS_INTER is to receive the indication interrupt of the system receiving and transmitting information and the sending process and receiving process prompt the MCU status or control TIME_SLOT_INTER is a 30ms time slot interrupt This interrupt is generated cyclically aft...

Page 17: ...rface The interface timing is as follows OMISSIS Figure 4 14 I2S Interface Timing among them 1 The LRCK clock frequency is determined by the Codec clock frequency and registers 0x32 0x33 By default the LRCK clock frequency is 8KHz LRCK clock frequency Codec clock frequency 2 parameter value 1 where the parameter value is derived from register 0x32 value register 0x33 value 2 The BCLK clock frequen...

Page 18: ...ACDAT pin multiplexing The definition is the same as LRCK multiplexing As shown in the figure below the control of the LRCK pin is taken as an example to illustrate the control diagram of the high and low levels The other pin control methods are the same as this OMISSIS Figure 4 15 LRCK pin multiplexing for general IO control interface timing 4 6 Vocoder HR_C6000 can seamlessly interface with voco...

Page 19: ...nd HR_C6000 and MCU is shown in the figure OMISSIS Figure 4 18 HR_V3000 vocoder and HR_C6000 connection block diagram OMISSIS Figure 4 19 shows the interface timing of I2S I2S operates in master mode and needs to configure the I2S_CK_M clock frequency via Register 0x2F calculated as codec operating frequency 2 Register 0x2F value 1 The I2S_FS_M clock frequency is configured by Register 0x32 0x33 t...

Page 20: ...lly control the DAC according to the transmission time slot or the MCU can control the working state of the DAC by configuring Bit5 and Bit4 Table 4 5HR_C6000 Baseband Transmit Control Register Address Address Function 0x01 Bit7 selects the correspondence between the HR_C6000 transmit port and the RF transmit port Bit 5 4 selects one of the four transmit modes 2 b00 means to send the intermediate ...

Page 21: ...Define two point modulation offset adjustment value a total of 10bit where the high 2bit is defined in the lower 2bit of reg0x48 0x48 Bit 1 0 defines two point modulation offset adjustment value a total of 10bit of which the lower 8bit is defined in reg0x47 4 7 1 Baseband IQ modulation OMISSIS 4 7 2 Two point modulation OMISSIS 4 7 3 IF IQ modulation OMISSIS 4 7 4 IF modulation OMISSIS 4 8 Receivi...

Page 22: ...se these application functions and only need to configure the corresponding function registers so that all DMR protocol customized voice and data services can be quickly and conveniently used The HR_C6000 is mainly developed based on the Layer 2 mode The user does not need to pay attention to the codec interleaving of the channel and the underlying modulation and demodulation process 5 1 Interrupt...

Page 23: ...tatus register indicates six interrupts that generate the end of the transmission including Bit7 indicates that the service transmission is completely terminated including voice and data The MCU distinguishes whether the voice or data is sent this time Confirming that the data service is received is the response packet that receives the correct feedback Bit6 Indicates that a Fragment length confir...

Page 24: ...interrupt In DMR mode this interrupt has sub status register 0x90 which has three types 1 0x80 indicates that the entire information is received and verified After the service data is verified the MCU extracts the data after the address 0x30 in the RX terminal 1 2KRAM through the SPI port The length of the data is defined by the corresponding field of the received frame header 2 0x00 indicates the...

Page 25: ...nding bit clear interrupt Waiting for interruption OMISSIS Figure 5 2 Interrupt Response Tree The Time_slot_inte interrupt is a TDMA time slot interrupt When the synchronization time slot of HR_C6000 is established the interrupt is continuously given at intervals of 30ms Until the synchronization is lost 5 2 Interface read and write instructions The user accesses through the general U_SPI includes...

Page 26: ...d 6 1 b0 Addr represents 8bits high order first and the read write start address is Addr When Cmd 6 1 b1 Addr indicates 16bits high order first and the read write start address is Addr 2 0 Addr 15 8 1 Write 0x01 to register 0x80 of the register system parameter table The format is Cmd Data 8 b 0 0000 100 8 b1000 0000 2 read the end 1 2KRAM from 0x30 2 bytes of data data content is 0x01 0x02 format...

Page 27: ... Voice Terminator 0x00 0x0b 0x00 0x08 A total of 72bit is the control letter 0x09 0x0b A total of 24 bits is the check information and the MCU is optional CSBK 0x00 0x0b 0x00 0x09 A total of 80 bits is the control information 0x0a 0x0b A total of 16 bits is the check information and the MCU is optional MBC Header 0x00 0x0b 0x00 0x09 A total of 80 bits is the control information 0x0a 0x0b A total o...

Page 28: ...bit control information Test send 0x00 0x48 Send mode test to store data address FM data address 1 0x030 0x22f A total of 512 bytes of data information You can send voice data for externally written FM or internally send voice data from Codec FM data address 2 0x230 0x42f A total of 512 bytes of data information You can send voice data for externally written FM or internally send voice data from C...

Page 29: ... length BPTC encoding interleaving and joins into 4 time slots 128bit Table 5 3 Group Call 72bit LC Information Sheet Information element Length Remark Protect Flag PF 1 Reserved 1 This bit shall be set to 0 Full Link Control Opcode FLCO 6 Shall be set to 000000 Feature set ID FID 8 Shall be set to 00000000 Service Option 8 Group address 24 Source address 24 Table 5 4 Call 72bit LC Information She...

Page 30: ...ce Head frame B Supports the construction of ShortLC packets with 72bitLC information for embedding into the EMB area of voice C Support for dynamic update of LC packages 3 CSBK packages MBC packages and data packets are supported detailed internals include A Support to join Slot Type 20bit including CC DataType for Golay 20 8 encoding B Support SYNC to join C Supports adding 80bit CSBK CRC16bit c...

Page 31: ...TC 196 96 encoding and interleaving F Supports the addition of 96bit MBC data for BPTC 196 96 encoding and interleaving G Support for adding 80bitMBC lastBlock performing CRC16bit check BPTC 196 96 encoding and interleaving H Support data packet header add 80bit data perform CRC16bit check add CRC mask perform BPTC 196 96 encoding and interleaving Figure 5 7 Unconfirmed packet header ...

Page 32: ...1 2 mode adds 96 bit data and performs BPTC 196 96 encoding and interleaving K Supports the last slot data of Rate 1 2 mode adds 64 bit data performs 32 bit CRC check checks all data performs BPTC 196 96 encoding and interleaving L Supports the data format of Rate 3 4 mode adds 96 bit data performs Trellis encoding and interleaving M Supports the last slot data of Rate 3 4 mode adds 64 bit data pe...

Page 33: ...ta perform BPTC 196 96 encoding and interleaving CC PI LCSS RC Info FEC Parity RC Info FEC Parity SYNC SYNC SYNC SYNC SYNC SYNC RC Info FEC Parity RC Info FEC Parity EMB Parity SYNC 48 10ms 30ms OMISSIS Figure 5 9 Independent RC frame structure 4 Supports RC signals for time slots RC and EMB A Support for adding 7bitEMB for QR 16 7 6 encoding B Support for adding 11bit RC signals performing variab...

Page 34: ...er reg0x40 is 0x43 and reg0x41 is 0x40 The system is configured in the passive receive state by default Other configurations are OK by default The transmit frame type configuration is specified by the reg0x50 register Table 5 5 Frame Type Coding Correspondence Slot frame type LocalDataType Whether voice Voice LC Header 0001 0 Voice PI Header 0000 0 Voice A 0000 1 Voice B 0001 1 Voice C 0010 1 Voic...

Page 35: ...formation and then generate a 16 bit parity bit according to a self defined verification method and write a total of 96 bits of information to the address of the transmission RAM of the HR_C6000 Address 11 then HR_C6000 takes this data directly for BPTC encoding and subsequent framing If it is a user defined frame type the verification information bits generated by the verification are stored in t...

Page 36: ...ers the receiving state The system starts to establish synchronization according to the synchronization information of the received signal and continues to receive synchronization information according to the received information To adjust the synchronization timeline to provide a 30ms approximate interrupt to the MCU After the complete time axis is established the chip has the conditions for send...

Page 37: ...OT_INTER interrupt and before position 2 Rdy_lst_inter interrupt the chip will give RF_RX_INTER for the CPU to set the RF channel correlation parameter According to the active passive mode established by the time axis the transmission and reception mode control of the time slot of the whole machine is combined into a working mode 1 Active sending Active sending means that the system is currently i...

Page 38: ...eceive TIME_SLOT_INTER T2 T1 t3 Rdy_lst_Inter software preparation data last time interrupt prompt Sys_Inter t1 1 7ms t2 27ms t3 4ms The t1 time is the start time of the chip sending code group frame t2 is the software preparation data and the configuration transceiver control command time and t3 is the interrupt for providing data to the mcu after the chip parsing data is completed In addition th...

Page 39: ...l the RF module In the passive mode the synchronization mechanism guarantees that if there is receiving synchronization information and the gap with the existing local synchronization is within 1 25ms real time synchronization adjustment will be performed if the reception synchronization disappears the reception signal disappears and the control does not control 0x41 for reception the chip Accordi...

Page 40: ...ayer 2 mode include voice transmission data transmission voice reception and data reception Data transmission 1 Configure reg0x10 to be 0x6A at power on and set the system to Layer 2 non relay mode 2 After receiving the send request button or other means configure reg0x40 to 0xA3 and set it to active mode 3 After receiving a 30ms interrupt the MCU configures reg0x41 to be 0x80 and reg0x50 to 0x60 ...

Page 41: ... to 0x00 In addition each time sys_inter is received reg0x52 and reg0x51 are read to determine the state and nature of each frame of data and the 96 bit data of 0x00 0x0B of the receiving end RAM is read to obtain the content of the received data frame Voice transmission 1 On power on configure reg0x10 to 0x6A set the system to Layer 2 non relay mode and register 0x06 to 0x45 The vocoder is contro...

Page 42: ...s0x05 3 When the next 30ms interrupt arrives configure reg0x41 to 0x00 The next time slot is not the received working time slot The receiving is closed If the address matches the configuration register 0x22 is configured to 0x20 and the vocoder decoding switch is turned on 4 When the next 30ms arrives configure reg0x41 to 0x50 enable the next time slot to receive enable and turn on the voice strea...

Page 43: ...48bit Data 196bit SYNC EMB RC 48bit Voice 216bit SYNC 48bit Data 48bit Figure 5 15 Receive Data Frame Type Format 2 Register settings Realize the bit error rate test function in one layer mode the register that needs to be configured is Realize the bit error rate test function in one layer mode the registers that need to be configured are Table 5 6 One layer mode error rate test control register a...

Page 44: ...nd the analog transmit channel is opened by configuring register 0x60 0x80 The speech is sampled and converted into a digital signal by the ADC in Codec After the HR_C6000 internal compression and weighting module performs audio signal processing it passes through the 12 5KHz 25KHz channel filter to improve the ACPR of the transmitted signal The transmission of voice and signaling such as analog v...

Page 45: ...or s 0dB compression point by configuring Register 0x2D 3 0 Aggravation The HR_C6000 provides an optional weighting module that meets the requirements of the TIA The weighting module processes the audio signal in the 300Hz to 3000Hz band at 6dB Oct The weighting module can be turned on by configuring register 0x34 5 1 b1 OMISSIS Figure 6 4 Weighted frequency response curve Filter The HR_C6000 prov...

Page 46: ...e FM modulator to obtain the modulation phase value and the baseband modulation to form the CDCSS Baseband signal output Figure 6 6 Transmitter system block diagram Detailed usage is detailed in Appendix A2 2 2 6 1 3 DTMF sending The DTMF signal is generated by a combination of four sets of high frequency signals and four sets of low frequency signals The low frequency signal is 2 5 dB lower than ...

Page 47: ...00 is in receive mode The HR_C6000 filters and receives the received IQ or intermediate frequency signal and sends it to the FM processing module The phase detected signal is filtered by an audio filter and then processed by Codec after an optional de emphasis and decompression module The above analog channels mainly support the reception of voice and signaling such as analog voice analog digital ...

Page 48: ...ugh the phase detector and the DC offset of the signal is cancelled by the frequency offset calibration module After the limiting processing the high frequency audio portion is filtered by the 4th order IIR 300Hz low pass filter The frequency response amplitude detection result is compared with the preset threshold value When the threshold is greater than the threshold the voice enable is enabled ...

Page 49: ...s and the detection end flag information is valid all the previously stored DTMF codes are combined into one frame output Figure 6 13 DTMF Receive Block Diagram The detailed usage is detailed in Appendix A2 2 3 6 2 4 2 tone reception 2 tone s demodulation mechanism is similar to address matching and the voice path can only be turned on when 2 tone matches the receive address setting 2 tone contain...

Page 50: ...vided into front end data acquisition and back end baseband signal processing The front end data collection part is similar to the second half of the sending end and will not be described here In the back end signal processing part key steps such as arrival detection timing synchronization and decision are all completed in this part The flow of MSK baseband processing is shown in Figure 7 2 OMISSI...

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