REV.-A
Table A-5. APD7810/7811 Port Functions
Pin
Signal
Direction
Description
1 - 8
P A O - 7
In/Out
A. Eight-bit
with output latch.
possible by mode A
(MA) register. Output HIGH.
9 - 1 6
PBO - 7
In/Out
B. Eight-bit
with output latch.
possible by mode B
register (MB). Output HIGH.
1 7 - 2 4
Pco - 7
In/Out
Port C. Eight-bit l/O with output latch. Port/control mode can be
set by mode control C
register. Output HIGH.
25
In
interrupt of the edge trigger (trailing edge).
26
1
In
Maskable interrupt input of the edge trigger (leading edge). Also
used as the AC input zero cross detecting terminal.
27, 29
MODE 1, 0
In/Out
781 1: O = LOW and 1 = HIGH
7810 modes set in accordance with external memory (see Table
A-2).
28
RESET
In
LOW reset
31
x2, xl
—
Crystal connection for built-in clock pulse. When clock pulses are
supplied externally, input must be to Xl.
32
.
Supply voltage,
33
—
Analog
3 4 - 4 1
- 7
Eight analog inputs of the A/D converter.
-4 can be used
as the input terminals to detect the leading edge and to set the
test flag upon detection of the trailing edge.
42
VAref
In
Reference voltage
43
—
Analog
44
out
Read strobe. LOW at the read machine cycle and at reset, HIGH
at other times.
45
WR
out
Write strobe. LOW during the write machine cycle and at reset,
HIGH at other times.
46
ALE
out
Address latch enable. Latches the lower 8 address bits to access
external memory.
4 7 - 5 4
PFO -7
Port F
781 1: Port bit-by-bit
possible by mode F register. In exten-
sion mode, gradual address output assignment is possible in
accordance with the size of external memory. See Table A-3.
78 10: By setting modes O and 1, assignment to the address bus
(AB 15 - 8) can be made in accordance with the size of the
external memory. The remaining terminals can be used as
ports. See Table A-4.
5 5 - 6 2
P D O - 7
Port D.
781 1: Port bit-by-bit
possible.
In extension mode,
act as the multiplexed address/data
bus
78 10: Multiplexed address/data bus to access external memory.
63
—
Supply voltage,
64
—
Supply voltage,
A-5
