2.4.7.2
Drive Pulse Width Control Circuit
In order to keep the value of the
drive pulse width constant, the
monitors the +24
line, the
common voltage, and uses the voltage
to adjust the width of the FIRE signal.
The
drive pulse width is controlled to be within the area shown by the oblique lines in Figure
I
425
400
I
405
350
i
I
350
I
I
I
I
I
I
I
I
1
I
I
I
I
I
I
I
I
I
345
325
I
1
I
300
I
,
,
21.6
24
26.4
Driving Voltage
Fig. 2-30.
Drive Pulse Width Range
2 . 2 K
4 2
4
+ 5 + 2 4
t
o
\
43
I
Fig. 2-31. +24
Monitor Circuit
The CPU monitors the +24 V line at
of the 8-bit analog to digital converter, computes the result,
and controls the drive pulse width of the signal (FIRE) output from the event timer. 4.7 V is applied to
reference voltage input
by ZD3, and the voltage obtained by di24 V by
and
(approximately 4.08 V at
is input to
2-33