Functions of the E05A03 gate array
are as follows:
1. Address latch
The gate array latches data on address data lines
-
at the leading edge of the ALE signal,
and outputs it to
-
(when ALE is high, the data is passed through without latching.)
2. Address mapping
The gate array inputs an address on AB 13- AB 15, and selects
1 or CS2 or enables the R/W mode
of this gate array using internal decoder 2.
3. Handshaking
●
The gate array latches data on
-
at the leading edge of the STROBE signal, and automatically
outputs the BUSY signal. The BUSY signal
is latched by the timing register to inform the CPU
that data has been transmitted to the CPU.
●
The timing for the BUSY signal, which is set at either the trailing or leading edge of the STROBE
signal, is selected by the control program (firmware).
●
The BUSY signal output from the timing register is
with the BUSY signal controlled by
the firmware.
4.
solenoid drive pulse
. When the FIRE signal from the CPU is brought Low, the data that was previously latched is output
on HD 1 -
to drive the corresponding solenoids in the
●
When FIRE is high,
-
are all
5. Shift register
●
This gate array includes a shift register
3), and the MSB (Most Significant Bit) can be read
by accessing the specified address
once. The data is shifted one bit to the left at the leading
edge of the
signal.
6. Initialization
When the INIT or
signal is low, the gate array sets
low and initializes the following.
●
latch (HD 1 -
are all set low even if FIRE is low.)
●
PF motor latch (PFA - PFD) are all set low.)
●
CR motor latch (CRA - CRD) are all set high.)
. Timing generator (enters the state indicating that no data has been received.)
●
Control latch (BUSY is set high (software-BUSY), PE is set low, and PELP, NLQLP, and CNDLP are set
high.)
7. Address decoder 2
Address decoder 2 selects one of the twelve modes listed in Table 2-13 according to the combination
of lower address bits OOH - 07H,
and
2 - 1 5
