
Embedian, Inc.
94
SMARC-iMX8M Computer on Module User’s Manual v.1.0
NXP i.MX8M CPU
JTAG(Connector: JST
SM10B‐SRSS‐TB, 1mm
pitch R/A SMD
Header)
Type
Note
Ball
Mode
Pin Name
Pin#
Pin Name
JTAG
1
VDD_33A
Power
JTAG I/O Voltage
(sourced by
Module)
U6
ATL0
JTAG_TRST_B
2
nTRST
I
JTAG Reset, active
low
V5
ALT0
JTAG_TMS
3
TMS
I
JTAG mode select
U5
ALT0
JTAG_TDO
4
TDO
O
JTAG data out
W5
ALT0
JTAG_TDI
5
TDI
I
JTAG data in
T5
ALT0
JTAG_TCK
6
TCK
I
JTAG clock
7
RTCK
I
JTAG return clock
8
GND
Ground
Ground
9
MFG_Mode#
I
Pulled low to
allow in‐circuit SPI
ROM update
10
GND
Ground
Ground