Embedian SMARC-iMX8M Series, User Manual, Page: 52 / 174

Embedian, Inc.
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SMARC-iMX8M Computer on Module User’s Manual v.1.0
2.1.10. PCIe_A and PCIe_B Interfaces
The SMARC‐iMX8M offers two PCI Express x1 lanes. The PCIe signals are
routed from the NXP® i.MX8M processor to the PCI Express port A and B of
the SMARC‐iMX8M edge finger. These signals support PCI Express Gen. 2.1
interfaces at 5 Gb/s and are backward compatible to Gen. 1.1 interfaces at
2.5 Gb/s. Only x1
PCI Express link configuration is possible. Diodes
PI6CFGL201B clock generators are used on each PCIe port to make PCIe
reference clock HCSL signals.
The following figure shows the PCIE port A and B block diagram.
Figure 7. PCI Express Block Diagram