Embedian SMARC-iMX8M Series, User Manual, Page: 125 / 174

Embedian, Inc.
125
SMARC-iMX8M Computer on Module User’s Manual v.1.0
SMARC Edge Finger NXP i.MX8M CPU Type Description
Pin# Pin Name Ball Mode Signal Name
P54 ESPI1_CS0# H19 ALT1
NAND_CE0_B__
QSPI_A_SS0_B
O SPI1 Master Chip
Select 0 output
P55 ESPI1_CS1# G21 ALT1 NAND_CE1_B__
QSPI_A_SS1_B O SPI1 Master Chip
Select 1 output
P56 ESPI1_CK G19 ALT1 NAND_ALE__
QSPI_A_SCLK O SPI1 Master Clock
output
P57 ESPI1_IO_1 J20 ALT1 NAND_DATA01__
QSPI_A_DATA01 I SPI1 Master Data
input (input to CPU,
output from SPI
device)
P58 ESPI1_IO_0 G20 ALT1 NAND_DATA00__
QSPI_A_DATA00 O SPI1 Master Data
output (output
from CPU, input to
SPI device)
P59 GND P Ground
P60
USB0+ A14 USB1_DP AIO
Differential USB0
data
P61 USB0‐ B14 USB1_DN AIO Differential USB0
data
P62 USB0_EN_OC# L20 ALT5 NAND_DATA04__
GPIO3_IO10 IO
OD Pulled low by
Module OD driver
to disable USB0
power.
Pulled low by
Carrier OD driver
to indicate
over‐current
situation
If this signal is
used, a pull‐up is
required on the
Carrier