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Embedian SMARC-iMX8M Series User Manual Download Page 14

Embedian, Inc. 

14 

SMARC-iMX8M Computer on Module User’s Manual v.1.0 

1.3 Block Diagram 

The  following  diagram  illustrates  the  system  organization  of  the 

SMARC‐iMX8M

. Arrows indicate direction of control and not necessarily signal 

flow.   

Figure 1: SMARC‐iMX8M Block Diagram 

Details for this diagram will be explained in the following chapters. 

Summary of Contents for SMARC-iMX8M Series

Page 1: ...rtex A53 and Cortex M4 24bits dual channel LVDS HDMI 2 0a DP 4 x COM Ports 1 x SDHC 1 x USB Host 2 0 1 x USB 2 0 OTG 2 x USB3 0 1 x 10 100 1000M Gigabit Ethernet 2 x CAN Bus 2 x SPIs 5 x I2Cs 12 bit G...

Page 2: ...Embedian Inc 2 SMARC iMX8M Computer on Module User s Manual v 1 0...

Page 3: ...Embedian Inc 3 SMARC iMX8M Computer on Module User s Manual v 1 0 Revision History Revision Date Changes from Previous Revision 1 0 2018 08 28 Initial Release...

Page 4: ...any language or computer language in any form or by any means electronic mechanical photocopying recording or otherwise without the express written permission of EMBEDIAN Trademarks The following list...

Page 5: ...aintenance EMBEDIAN will not be responsible for any defects or damages to other products not supplied by EMBEDIAN that are caused by a faulty EMBEDIAN product Technical Support Technicians and enginee...

Page 6: ...IMX8M GENERAL FUNCTIONS 20 2 2 SMARC IMX8M DEBUG 97 2 3 MECHANICAL SPECIFICATIONS 97 2 4 ELECTRICAL SPECIFICATIONS 113 2 5 ENVIRONMENTAL SPECIFICATIONS 116 CHAPTER 3 CONNECTOR PINOUT 118 3 1 SMARC IM...

Page 7: ...les and document titles monospaced type Filenames pathnames and code examples Embedian Information Document Updates Please always check the product specific section on the Embedian support website at...

Page 8: ...n Inc 8 SMARC iMX8M Computer on Module User s Manual v 1 0 Additional Resources Please also refer to the most recent NXP i MX8M processor reference manual and related documentation for additional info...

Page 9: ...r s Manual v 1 0 Introduction This Chapter gives background information on the SMARC iMX8M Section include Features and Functionality Module Variant Block diagram Software Support Hardware Abstraction...

Page 10: ...14 pin 0 5mm pitch right angle connector this connector is sometimes identified as an 321 pin connector but 7 pins are lost to the key Featuring NXP s i MX8M System on Chip Embedian s SMARC iMX8M offe...

Page 11: ...M ARM Cortex A53 and Cortex M4 up to 1 5GHz Memory Onboard 8GB eMMC Flash Onboard 2GB or 4GB LPDDR4 Networking 1 x 10 100 1000 Mbps Ethernet Display Single channel LVDS LCD 24 bit or dual channel LVDS...

Page 12: ...an Inc 12 SMARC iMX8M Computer on Module User s Manual v 1 0 4W Thermal Commercial Temperature 0o C 80o C Industrial Temperature 40o 85o C Power Supply 3V to 5 25V 1 8V module IO support SMARC 2 0 com...

Page 13: ...re CPU running up to 4 x 1 5GHz Q quad core CPU running up to 4 x 1 5GHz 2 2G 2GB LPDDR4 memory 4G 4GB LPDDR4 memory 3 I Industrial temperature 40o C 85o C for 2GB LPDDR4 and 30o C 85o C for 4GB LPDDR...

Page 14: ...1 3 Block Diagram The following diagram illustrates the system organization of the SMARC iMX8M Arrows indicate direction of control and not necessarily signal flow Figure 1 SMARC iMX8M Block Diagram D...

Page 15: ...l with I O at the register level 1 5 Document and Standard References 1 5 1 External Industry Standard Documents eMMC Embedded Multi Media Card the eMMC electrical standard is defined by JEDEC JESD84...

Page 16: ...802 3ab www ieee org HDMI Specification Version 1 3a November 10 2006 Hitachi and other companies www hdmi org RS 232 EIA Recommended Standard 232 this standard for asynchronous serial port data exch...

Page 17: ...SMARC Evaluation Carrier Board Schematic PDF and OrCAD format SMARC Evaluation Carrier Board User s Manual SMARC iMX8M User s Manual PinMux file for SMARC iMX8M SMARC iMX8M Schematic Checklist 1 5 4 N...

Page 18: ...essors 1 5 6 NXP Software Documents Linux 4 9 88_2 0 0 Android O8 1 0_1 3 0 8MQ GA Documentation 1 5 7 Embedian Software Documents Embedian Linux BSP for SMARC iMX8M Module Embedian Android BSP for SM...

Page 19: ...on Module User s Manual v 1 0 Specifications This Chapter provides SMARC iMX8M specifications Section include SMARC iMX8M General Functions SMARC iMX8M Debug Mechanical Specifications Electrical Spec...

Page 20: ...ssible SMARC iMX8M Feature Support SMARC iMX8M Feature Support Instances LVDS LCD Display Support 1 Yes 1 dual channel Note1 DP eDP 1 Yes 1Note2 HDMI Display Support 1 Yes 1 Serial Camera Support 2 Ye...

Page 21: ...interface 2 x 18 bpp OR 2 x 24 bpp up to 1 920 1 200 60 fps at 24 bpp Default configuration is single channel 24 bit To change this configuration users need to send i2c command to SN65DSI84 MIPI_DSI t...

Page 22: ...3 0 OpenVG and Vulkan GC7000Lite 4 shaders OpenGL ES 3 1 OpenCL 1 2 OpenGL 3 0 OpenVG and Vulkan GC7000Lite 4 shaders OpenGL ES 3 1 OpenCL 1 2 OpenGL 3 0 OpenVG and Vulkan VPU 4Kp60 HEVC H 265 H 264...

Page 23: ...ys boot up from the onboard eMMC flash first The firmware in eMMC flash will read the BOOT_SEL configuration from the boot selection and boot up the devices from that selected 2 1 5 Clocks A 25 MHz os...

Page 24: ...8M Cortex A53 processor passing through a TI SN65DSI84 MIPI DSI Bridge To FLATLINK LVDS Each channel consists of one clock pair and four data pairs The LVDS signals support the flow of MIPI DSI data f...

Page 25: ...Embedian Inc 25 SMARC iMX8M Computer on Module User s Manual v 1 0 The following figure shows the LVDS LCD block diagram Figure 2 SMARC iMX8M LVDS LCD Diagram...

Page 26: ...gured as an 18 bit 24 bit single channel LVDS output or a dual channel LVDS output by accessing TI SN65DSI84 0x18 register via I2C_GP bus The default configuration from software is 24 bit single chann...

Page 27: ...DSI_CLK A17 ALT0 MIPI_DSI_D0_N__ MIPI_DSI_D0_N J3 DA0N MIPI_DSI_D0 B17 ALT0 MIPI_DSI_D0_P__ MIPI_DSI_D0_P H3 DA0P MIPI_DSI_D0 A16 ALT0 MIPI_DSI_D1_N__ MIPI_DSI_D1_N J4 DA1N MIPI_DSI_D1 B16 ALT0 MIPI_D...

Page 28: ...0_0 eDP0_TX0 DSI0_D0 LVDS0_0 D8 A_Y1P S128 LVDS0_1 eDP0_TX1 DSI0_D1 LVDS0_1 LVDS0 LCD data channel differential pairs 2 D9 A_Y1N S129 LVDS0_1 eDP0_TX1 DSI0_D1 LVDS0_1 E8 A_Y2P S131 LVDS0_2 eDP0_TX2 DS...

Page 29: ...DP1_TX0 DSI1_D0 LVDS1_0 LVDS1 LCD data channel differential pairs 1 A3 B_Y0N S112 LVDS1_0 eDP1_TX0 DSI1_D0 LVDS1_0 B4 B_Y1P S114 LVDS1_1 eDP1_TX1 DSI1_D1 LVDS1_1 LVDS1 LCD data channel differential pa...

Page 30: ...l LVDS mode in order to receive odd and even pixel data 2 1 6 3 Other LCD Control Signals The signals in the table below support the LVDS LCD interfaces as these are created from the same i MX8M sourc...

Page 31: ...D EEPROMs 2 1 7 HDMI Interface High Definition Multimedia Interface HDMI is a licensable compact audio video connector interface for transmitting uncompressed digital streams HDMI encodes the video da...

Page 32: ...Embedian Inc 32 SMARC iMX8M Computer on Module User s Manual v 1 0 support The following figure shows the HDMI block diagram Figure 3 SMARC iMX8M HDMI Diagram...

Page 33: ...HDMI_TX_P_ LN_1 P95 HDMI_D1 DP1_LANE1 HDMI_D1 N1 N A HDMI_TX_M_ LN_2 P93 HDMI_D2 DP1_LANE0 HDMI_D2 TMDS HDMI data differential pair 2 N2 N A HDMI_TX_P_ LN_2 P92 HDMI_D2 DP1_LANE0 HDMI_D2 M2 N A HDMI_...

Page 34: ...8V HDMI Hot Plug Detect input HDMI_CTRL_DAT Bi Dir OD CMOS 1 8V I2C data line dedicated to HDMI HDMI_CTRL_CK Bi Dir OD CMOS 1 8V I2C clock line dedicated to HDMI HDMI displays uses 5V I2C signaling T...

Page 35: ...coupled but the DP_AUX pair must be AC coupled A set of FET switches is used on SMARC iMX8M to sort this out The FET gates are controlled by the AUX_SEL pin function The table below shows the AUX_SEL...

Page 36: ...r 0 3 positive DP1_LANE 0 3 Output AC Coupled off module DP Data Pair 0 3 negative DP1_HPD Input DC coupled CMOS 1 8V DP Hot Plug Detect input DP1_AUX Bi Dir AC Coupled on module DP AUX Channel part o...

Page 37: ...3 0 ports USB 2 3 The USB 2 0 and USB 3 0 IP in i MX8M processor are independent Per the SMARC specification the module supports a USB On The Go OTG port capable of functioning either as a client or...

Page 38: ...61 USB0 USB0 L20 ALT5 NAND_DATA04__ GPIO3_IO10 P62 USB0_EN_OC USB0_EN_OC USB0 power enable over current indication signal D14 Turn on USB_OTG_VBUS P63 USB0_VBUS_ DET USB0_VBUS_ DET USB0 host power det...

Page 39: ...STX USB2 transmit signal differential pair positive B13 USB1_TX_N S72 USB2_SSTX USB2_SSTX USB2 transmit signal differential pair negative A12 USB1_TX_P S74 USB2_SSRX USB2_SSRX USB2 receive signal diff...

Page 40: ...RX USB3 receive signal differential pair positive B13 USB1_TX_N S66 USB3_SSRX USB3_SSRX USB3 receive signal differential pair negative M19 ALT5 NAND_DATA07__ GPIO3_IO13 P74 USB3_EN_OC USB3_EN_OC USB3...

Page 41: ...he Module to a 3 3V rail The pull up rail may be switched off to conserve power if the USB port is not in use Further details may be found in Section 2 1 8 2 USBx_EN_OC Discussion below USB0_VBUS_DET...

Page 42: ...3 3V enable voltage level 2 The Module drives USB 0 3 _EN_OC low to disable the power delivery to the USBx device 3 The Module floats USB 0 3 _EN_OC to enable power delivery The line is pulled to 3 3V...

Page 43: ...the SMARC USB 0 3 _EN_OC lines Outputs driving the USBx_EN_OC lines are open drain The Carrier board USB power switch if present is enabled by USB 0 3 _EN_OC after a device connection is detected on...

Page 44: ...physical layer PHY transceiver with variable I O voltage that is compliant with the IEEE 802 3 2005 standards The AR8035 supports communication with an Ethernet MAC via a standard RGMII interface The...

Page 45: ...Embedian Inc 45 SMARC iMX8M Computer on Module User s Manual v 1 0 This is diagrammed below Figure 6 Gigabit Ethernet Connection from i MX8M to Qualcomm Atheros AR8035...

Page 46: ...ta bits that are sent by the transceiver on the receive path U21 ALT0 ENET_RD1__ ENET1RGMII_RD1 28 RXD1 RMII_RD1 Bit 1 of the 4 data bits that are sent by the transceiver on the receive path U20 ALT0...

Page 47: ...ransmits data to the transceiver using this signal R21 ALT0 ENET_TD1__ ENET1_RGMII_TD1 35 TXD1 RGMII_TD1 The MAC transmits data to the transceiver using this signal R19 ALT0 ENET_TD2__ ENET1_RGMII_TD2...

Page 48: ...al Transmit Receive Negative Channel 0 P28 GbE_CTREF GBE_CTREF Center tap reference voltage 12 TRXP1 P27 GbE_MDI1 GBE_MDI1 Differential Transmit Receive Positive Channel 1 13 TRXN1 P26 GbE_MDI1 GBE_MD...

Page 49: ...Activity Indication LED Driven low on Link 10 100 or 1000 mbps Blinks on Activity Could be able to sink 24mA or more Carrier LED current 24 LED_10_100 P21 GbE_LINK100 GBE_LINK100 Link Speed Indicatio...

Page 50: ...to magnetics Media Dependent Interface GBE_MDI3 GBE_MDI3 Bi Dir GBE_MDI Bi directional transmit receive pair 3 to magnetics Media Dependent Interface GBE_100 Output OD CMOS 3 3V Link Speed Indication...

Page 51: ...Configuration Halo HFJ11 1G02E Integrated RJ45 8 0o C 70o C HP Auto MDIX UDE RB1 BA6BT9WA Integrated RJ45 8 40o C 85o C HP Auto MDIX Halo TG1G S002NZRL 24 pin SOIC W 8 0o C 70o C HP Auto MDIX For ind...

Page 52: ...ss port A and B of the SMARC iMX8M edge finger These signals support PCI Express Gen 2 1 interfaces at 5 Gb s and are backward compatible to Gen 1 1 interfaces at 2 5 Gb s Only x1 PCI Express link con...

Page 53: ...t PCI Express Port A F21 ALT5 NAND_CE2_B__ GPIO3_IO3 P75 PCIE_A_RST PCIE_A_RST Reset Signal for external devices K25 PCIE1_REF_PAD _CLK_P P83 PCIE_A_REFCK PCIE_A_REFCK Differential PCI Express Referen...

Page 54: ...nal for external devices F25 PCIE2_REF_PAD _CLK_P S84 PCIE_B_REFCK PCIE_B_REFCK Differential PCI Express Reference Clock Signals for Lanes B F24 PCIE2_REF_PAD _CLK_P S85 PCIE_B_REFCK PCIE_B_REFCK D25...

Page 55: ...e Link A receive data pair 0 No coupling caps on Module PCIE_A_REFCK PCIE_A_REFCK Output HCSL PCIe Differential PCIe Link A reference clock output DC coupled PCIE_A_RST Output CMOS 3 3V PCIe Port A re...

Page 56: ...v 1 0 2 1 10 2 PCIe Wake Signals The table below shows the PCIe Wake signal Edge Golden Finder Signal Name Direction Type Tolerance Description PCIE_WAKE Input CMOS 3 3V PCIe wake up interrupt to host...

Page 57: ...sensitive signals to the camera Non time sensitive controls such as configuration reset are performed by the ARM platform through I2C interface or GPIO signals The SMARC specification defines serial a...

Page 58: ...Embedian Inc 58 SMARC iMX8M Computer on Module User s Manual v 1 0 The following figure shows the serial camera interface block diagram Figure 8 MIPI Serial Camera Interface Block Diagram...

Page 59: ...S12 CSI0_RX0 CSI0_D0 CSI0 differential data inputs B23 ALT0 MIPI_CSI1_D0_P S11 CSI0_RX0 CSI0_D0 C22 ALT0 MIPI_CSI1_D1_N S15 CSI0_RX1 CSI0_D1 D22 ALT0 MIPI_CSI1_D1_P S14 CSI0_RX1 CSI0_D1 MIPI Serial Ca...

Page 60: ...ess ranges NXP i MX8M CPU SMARC iMX8M Edge Golden Finger Net Names Note Ball Mode Pin Name Pin Pin Name I2C_CAM0 G7 ALT0 I2C2_SCL__ I2C2_SCL S5 CSI0_TX I2C_CAM0_CK I2C_CAM0_CK F7 ALT0 I2C2_SDA__ I2C2_...

Page 61: ...ta I2C_CAM1_CK Bi Dir OD CMOS 1 8V Serial camera support link I2C clock 2 1 11 2 MIPI Serial Camera In MIPI CSI0 1 Edge Golden Finder Signal Name Direction Type Tolerance Description MIPI_CSI0_D 0 1 M...

Page 62: ...bit eMMC support and the other one is used for external SDHC SDIO interface The SMARC iMX8M module supports one 4 bit SDIO interface per the SMARC 2 0 specification The SDIO interface uses 3 3V signa...

Page 63: ...SDHC2_ DATA2 P41 SDIO_D2 SDIO_D2 SDIO Data 2 P21 ALT0 SD2_DATA3__ SD2_USDHC2_ DATA3 P42 SDIO_D3 SDIO_D3 SDIO Data 3 M21 ALT5 SD2_WP__ GPIO2_IO20 P33 SDIO_WP SDIO_WP SDIO write protect signal M22 ALT0...

Page 64: ...The Carrier SDIO Card can be selected as the Boot Device See section 4 3 Edge Golden Finder Signal Name Direction Type Tolerance Description SDIO_D 0 3 Bi Dir CMOS 3 3V 4 bit data path SDIO_CMD Bi Dir...

Page 65: ...hip selects that can connect two SPI slave devices on each channel SPI devices will share the SPI0_DIN SPI0_DO and SPI0_CK pins but each device will have its own chip select pin The chip select signal...

Page 66: ...Embedian Inc 66 SMARC iMX8M Computer on Module User s Manual v 1 0 The SPI interface is diagramed below Figure 10 SPI Interface Block Diagram...

Page 67: ...output T6 ALT5 GPIO1_IO00__ GPIO1_IO0 P31 SPI0_CS1 SPI0_CS1 SPI0 Master Chip Select 1 output D5 ALT0 ECSPI1_SCLK__ ECSPI1_SCLK P44 SPI0_CK SPI0_SCLK SPI0 Master Clock output B4 ALT0 ECSPI1_MISO__ ECSP...

Page 68: ...Chip Select 1 output G19 ALT1 NAND_ALE__ QSPI_A_SCLK P56 ESPI_CK ESPI_SCLK QSPI Master Clock output G20 ALT1 NAND_DATA00__ QSPI_A_DATA00 P58 ESPI_IO_0 ESPI_IO_0 QSPI Master Data 0 J20 ALT1 NAND_DATA01...

Page 69: ...4 3 Boot Select Edge Golden Finder Signal Name Direction Type Tolerance Description SPI0_CS0 Output CMOS 1 8V SPI0 Master Chip Select 0 output SPI0_CS1 Output CMOS 1 8V SPI0 Master Chip Select 1 outpu...

Page 70: ...elect Edge Golden Finder Signal Name Direction Type Tolerance Description ESPI_CS0 Output CMOS 1 8V QSPI Master Chip Select 0 output ESPI_CS1 Output CMOS 1 8V QSPI Master Chip Select 1 output ESPI_CK...

Page 71: ...io signals These signals are derived from the Synchronous Audio Interface SAI of the NXP i MX8M processor The Serial Audio Interface SAI implements a synchronous serial bus interface for connecting di...

Page 72: ...LRCK I2S0_LRCK Left Right audio synchronization clock G5 ALT0 SAI2_TXD0__ SAI2_TX_DATA0 S40 I2S0_SDOUT I2S0_SDOUT Digital audio Output H6 ALT0 SAI2_RXD0__ SAI2_RX_DATA0 S41 I2S0_SDIN I2S0_SDIN Digital...

Page 73: ...ster clock output to Audio codecs I2S0 Signals I2S0_LRCK Bi Dir CMOS 1 8V Left Right audio synchronization clock I2S0_SDOUT Output CMOS 1 8V Digital audio Output I2S0_SDIN Input CMOS 1 8V Digital audi...

Page 74: ...t 1 8V levels The selection of 1 8V compatible transceivers is a bit limited although more are appearing with time Two such devices are the Texas Instruments TRS3253E and the Maxim MAX13235E illustrat...

Page 75: ...ER0_TX SER0_TX Asynchronous serial port data out C6 ALT0 UART4_RXD__ UART4_DCE_RX P130 SER0_RX SER0_RX Asynchronous serial port data in A5 ALT1 ECSPI2_SS0__ UART4_DCE_ RTS_B P131 SER0_RTS SER0_RTS Req...

Page 76: ...ART2_RXD__ UART2_DCE_RX P137 SER2_RX SER2_RX Asynchronous serial port data in E5 ALT5 ECSPI2_MOSI__ GPIO5_IO11 P138 SER2_RTS SER2_RTS Request to Send handshake line for SER2 C5 ALT5 ECSPI2_SCLK__ GPIO...

Page 77: ...e 2 wire ports data only Edge Golden Finder Signal Name Direction Type Tolerance Description SER 0 3 _TX Output CMOS 1 8V Asynchronous serial port data out SER 0 3 _RX Input CMOS 1 8V Asynchronous ser...

Page 78: ...ification PM Power Management LCD Liquid Crystal Display GP General Purpose CAM0 Camera 0 CAM1 Camera 1 and HDMI SMARC iMX8M does not have HDMI interface it defines five out of the six I2C buses and s...

Page 79: ...8V I2C_GP I2C3 General purpose use CMOS 1 8V I2C_LCD I2C2 LCD display support to read LCD display EDID EEPROMs for parallel and LVDS LCD General Purpose CMOS 1 8V I2C_CAM0 I2C2 Serial camera 0 Genera...

Page 80: ..._ I2C3_SCL S48 I2C_GP_CK I2C_GP_CK General purpose I2C bus clock E9 ALT0 I2C3_SDA__ I2C3_SDA S49 I2C_GP_DAT I2C_GP_DAT General purpose I2C bus data I2C_LCD G7 ALT0 I2C2_SCL__ I2C2_SCL S139 I2C_LCD_CK...

Page 81: ...0 NXP i MX8M CPU SMARC iMX8M Edge Golden Finger Net Names Note Ball Mode Pin Name Pin Pin Name I2C_HDMI F8 N A I2C4_SCL__ I2C4_SCL P105 HDMI_CTRL_ CK HDMI_CTRL_ CK HDMI I2C bus clock F8 N A I2C4_SDA_...

Page 82: ...enerator for PCIe Lane A 2 Pericom PI6CFGL201BZDIE PCIe Gen 1 2 3 Clock Generator 0x6A 0xD5 0XD4 Clock Generator for PCIe Lane B 2 NXP MC34PF4210A1ES PMIC 0x08 0x01 0x00 PMIC 3 Seiko S 35390A Real tim...

Page 83: ...th a high level of security The SMARC iMX8M module implements two CAN bus interfaces from Microchip MCP2515 SPI to CAN interface IC The SPI bus used to interface with MCP2515 CAN controller is SPI0 Th...

Page 84: ...Embedian Inc 84 SMARC iMX8M Computer on Module User s Manual v 1 0 The following figure shows the CAN bus block diagram Figure 12 SMARC iMX8M CAN Bus Diagram...

Page 85: ...is shown in the following table NXP i MX8M CPU Microchip MCP2515T Net Names Note Ball Mode Pin Name Pin Pin Name B4 ALT0 ECSPI1_MISO__ ECSPI1_MISO 15 SO SPI_CAN_SO A4 ALT0 ECSPI1_MOSI__ ECSPI1_MOSI 14...

Page 86: ...s shown in the following table NXP i MX8M CPU Microchip MCP2515T Net Names Note Ball Mode Pin Name Pin Pin Name B4 ALT0 ECSPI1_MISO__ ECSPI1_MISO 15 SO SPI_CAN_SO A4 ALT0 ECSPI1_MOSI__ ECSPI1_MOSI 14...

Page 87: ...naling should be supported on the Module GPIO8 P116 pin This is an active low input to the Module from the CAN bus transceiver CAN1 bus error condition signaling should be supported on the Module GPIO...

Page 88: ...al Name Direction Type Tolerance Description CAN0_TX Output CMOS 1 8V CAN0 Transmit output CAN0_RX Input CMOS 1 8V CAN0 Receive input 2 1 17 5 CAN1 BUS Signals Edge Golden Finder Signal Name Direction...

Page 89: ...Specific alternate functions are assigned to some GPIOs such as PWM Tachometer capability Camera support CAN Error Signaling and HD Audio reset All pins are capable of bi directional operation A defau...

Page 90: ...e low output M5 ALT5 SAI5_RXD0__ GPIO3_IO21 P111 GPIO3 CAM1_RST GPIO3 Camera 1 Reset active low output L4 ALT5 SAI5_RXD1__ GPIO3_IO22 P112 GPIO4 HDA_RST GPIO4 HD Audio Reset active low output F6 ALT5...

Page 91: ...itivity polarity are generally configurable in the i MX8M register set Edge Golden Finder Signal Name Preferre d Directio n Type Tolerance Description GPIO0 CAM0_PWR Output CMOS 1 8V Camera 0 Power En...

Page 92: ...the standard Linux Watchdog API A description of the API is available following the link below http www kernel org doc Documentation watchdog watchdog api txt WDT signals are exposed on the SMARC gold...

Page 93: ...and pin out Figure 13 JTAG Connector Location and Pinout JTAG functions for CPU debug and test are implemented on separate small form factor connector CN3 JST SM10B SRSS TB 1mm pitch R A SMD Header T...

Page 94: ...1 VDD_33A Power JTAG I O Voltage sourced by Module U6 ATL0 JTAG_TRST_B 2 nTRST I JTAG Reset active low V5 ALT0 JTAG_TMS 3 TMS I JTAG mode select U5 ALT0 JTAG_TDO 4 TDO O JTAG data out W5 ALT0 JTAG_TD...

Page 95: ...ial EEPROM is placed at I2C slave addresses A2 A1 A0 set to 0 I2C slave address 50 hex 7 bit address format or A0 A1 hex 8 bit format for I2C EEPROMs address bits A6 A5 A4 A3 are set to binary 0101 co...

Page 96: ...odule with Quad Lite Core and 4GB LPDDR4 Configuration Version 4 Hardware version code for version in ASCII 00A0 rev A0 Serial Number 12 Serial number of the board This is a 12 character string which...

Page 97: ...ation Carrier The default baud rate setting is 115 200 8N1 SER3 pin out of the SMARC iMX8M is shown below NXP i MX8M CPU SMARC iMX8M Edge Golden Finger Net Names Notes mode Pin Name Pin Pin Name SER3...

Page 98: ...without PCB complied with SMARC specification defines as 1 3mm as the maximum 2 3 4 Mechanical Drawings The mechanical information is shown in Figure 14 SMARC iMX8M Mechanical Drawings Top View and F...

Page 99: ...omputer on Module User s Manual v 1 0 Figure 15 SMARC iMX8M Mechanical Drawings Bottom View The figure on the following page details the 82mm x 50mm Module mechanical attributes including the pin numb...

Page 100: ...Embedian Inc 100 SMARC iMX8M Computer on Module User s Manual v 1 0 Figure 16 SMARC iMX8M Module Mechanical Outline...

Page 101: ...Inc 101 SMARC iMX8M Computer on Module User s Manual v 1 0 Top side major component IC and Connector information is shown in Figure 17 SMARC iMX8M Top side components Figure 17 SMARC iMX8M Top Side Co...

Page 102: ...102 SMARC iMX8M Computer on Module User s Manual v 1 0 Bottom side major component IC and Connector information is shown in Figure 18 SMARC iMX8M Bottom side components Figure 18 SMARC iMX8M Bottom Si...

Page 103: ...ck height Carrier board connector is used there shall not be components on the Carrier board Top side in the Module region Additionally when 1 5mm stack height connectors are used there should not be...

Page 104: ...3 5 Carrier Board Connector PCB Footprint Figure 20 Carrier Board Connector PCB Footprint Note The hole diameter for the 4 holes 82mm x 50mm Module or 7 holes 82mm x 80mm Module depends on the spacer...

Page 105: ...7 Carrier Board Standoffs Figure 21 Screw Fixation Standoffs secured to the Carrier board are expected The standoffs are to be used with M2 5 hardware Most implementations will use Carrier board stand...

Page 106: ...custom part with 1 5mm standoff length M2 5 internal thread and 5 56mm standoff OD is available from PEM The Carrier PCB requires a 4 22mm hole and 6 2mm pad to accept these parts Other vendors such a...

Page 107: ...5mm 4 3mm Flash Std Black Foxconn AS0B821 S43N H 1 5mm 4 3mm Flash Std Ivory Foxconn AS0B826 S43B H 1 5mm 4 3mm 10 u in Std Black Foxconn AS0B826 S43N H 1 5mm 4 3mm 10 u in Std Ivory Lotes AAA MXM 008...

Page 108: ...2mm Flash Std Tan Speedtech B35P101 02122 H 2 76mm 5 2mm 10 u in Std Black Speedtech B35P101 02022 H 2 76mm 5 2mm 10 u in Std Tan Speedtech B35P101 02123 H 2 76mm 5 2mm 15 u in Std Black Speedtech B3...

Page 109: ...these pins to allow more signal pins Footprint and pin numbering information for application of this 314 pin connector to SMARC is given in the sections below 2 3 9 Module Cooling Solution Heat Spread...

Page 110: ...thickness details of the TIM vary from design to design The two holes immediately adjacent to the TIM serve to secure the PCB in the SOC area and compress the TIM The four interior holes that are fur...

Page 111: ...Computer on Module User s Manual v 1 0 Dimensions in the figure above are in millimeters TIM stands for Thermal Interface Material The TIM takes up the small gap between the SOC top and the Module fac...

Page 112: ...te to be flush with a secondary heat sink Hole size depends on standoffs used Standoff diameter must be compatible with SMARC Module mounting hole pad and hole size 6 0mm pads 2 7mm holes on the Modul...

Page 113: ...e VDD_RTC pin from the carrier board This connection provides back up power to the module PMIC The RTC is powered via the primary system 3 3V supply during normal operation and via the VBAT power inpu...

Page 114: ...t water exposure etc lower MTBF values 2 4 6 Power Consumption The power consumption values listed in this document were measured under a controlled environment The hardware used for testing includes...

Page 115: ...mately 100 C peak power consumption Note With the linux stress tool we stressed the CPU to maximum frequency The table below provides additional information about the different variants offered by the...

Page 116: ...o 80 C air temperature without a passive heat sink arrangement Industrial temperature 40o C 85o C is also available with different part number SMARC iMX8M X XX I 2 5 2 Humidity Operating 10 to 90 RH n...

Page 117: ...an Inc 117 SMARC iMX8M Computer on Module User s Manual v 1 0 Connector PinOut This Chapter gives detail pinout of SMARC iMX8M golden finger edge connector Section include SMARC iMX8M Connector Pin Ma...

Page 118: ...e key 4 on the primary side and 3 on secondary side The Secondary Bottom side faces the Carrier board when a normal or standard Carrier connector is used The SMARC iMX8M module pins are deliberately n...

Page 119: ...ecification The NXP i MX8M CPU column shows the connection of the CPU signals on the module The format of this column is Ball Mode Signal Name where Signal Name is the chip where the signals are conne...

Page 120: ...differential data inputs 0 positive P8 CSI1_RX0 C20 MIPI_CSI2_D0_ N I CSI1 differential data input 0 negative P9 GND P Ground P10 CSI1_RX1 B20 MIPI_CSI2_D1_ P I CSI1 differential data input 1 positive...

Page 121: ...bE0_LINK100 O OD Link Speed Indication LED for 100Mbps Could be able to sink 24mA or more Carrier LED current P22 GbE0_LINK1000 O OD Link Speed Indication LED for 1000Mbps Could be able to sink 24mA o...

Page 122: ...ential Transmit Receive Negative Channel 1 P27 GbE0_MDI1 AIO Qualcomm AR8035 Differential Transmit Receive Positive Channel 1 P28 GbE0_CTREF O Qualcomm AR8035 Center tap reference voltage for GBE Carr...

Page 123: ...O_CMD M22 ALT0 SD2_CMD__ SD2_USDHC2_ CMD IO Command Line P35 SDIO_CD L21 ALT5 SD1_CD__ GPIO2_IO12 I Card Detect P36 SDIO_CK L22 ALT0 SD2_CLK__ SD2_USDHC2_ CLK O Clock P37 SDIO_PWR_EN R22 ALT5 SD2_RESE...

Page 124: ...put P44 SPI0_CK D5 ALT0 ECSPI1_SCLK__ ECSPI1_SCLK O SPI0 Master Clock output P45 SPI0_DIN B4 ALT0 ECSPI1_MISO__ ECSPI1_MISO I SPI0 Master Data input input to CPU output from SPI device P46 SPI0_DO A4...

Page 125: ...k output P57 ESPI1_IO_1 J20 ALT1 NAND_DATA01__ QSPI_A_DATA01 I SPI1 Master Data input input to CPU output from SPI device P58 ESPI1_IO_0 G20 ALT1 NAND_DATA00__ QSPI_A_DATA00 O SPI1 Master Data output...

Page 126: ...sed as a device P64 USB0_OTG_ID C14 USB1_ID I USB OTG ID input active high P65 USB1 A10 USB_H1_DP IO Differential USB0 data pair P66 USB1 B10 USB_H1_DN IO P67 USB1_EN_OC J22 ALT5 NAND_DATA05__ GPIO3_I...

Page 127: ...OD driver to disable USB0 power Pulled low by Carrier OD driver to indicate over current situation If this signal is used a pull up is required on the Carrier P72 RSVD Not used P73 RSVD Not used P74 U...

Page 128: ...P Ground P83 PCIE_A_REFCK K25 PCIE1_REF_PAD_ CLK_P O Differential PCI Express Reference Clock Signals for Lanes A P84 PCIE_A_REFCK K24 PCIE1_REF_PAD_ CLK_P O Differential PCI Express Reference Clock S...

Page 129: ...E0 N2 N A HDMI_TX_P_ LN_2 O TMDS HDMI data differential pair 2 DP Data Pair 0 P93 HDMI_D2 DP1_LANE0 N1 N A HDMI_TX_M_ LN_2 O TMDS HDMI data differential pair 2 DP Data Pair 0 P94 GND P Ground P95 HDMI...

Page 130: ...P100 GND P Ground P101 HDMI_CK DP1_LANE3 M1 N A HDMI_TX_P_ LN_3 O HDMI differential clock output pair P102 HDMI_CK DP1_LANE3 M2 N A HDMI_TX_M_ LN_3 O HDMI differential clock output pair P103 GND P Gr...

Page 131: ...XD0__ GPIO3_IO21 IO Camera 1 Reset active low output P112 GPIO4 HDA_RST L4 ALT5 SAI5_RXD1__ GPIO3_IO22 IO HD Audio Reset active low output P113 GPIO5 PWM_OUT F6 ALT5 SPDIF_TX__ GPIO5_IO3 IO PWM output...

Page 132: ...anagement I2C bus data P123 BOOT_SEL0 P5 ALT0 GPIO1_IO04__ GPIO1_IO4 I SYSBOOT and Line De multiplexer Logic Pulled up on Module Driven by OD part on Carrier P124 BOOT_SEL1 P7 ALT0 GPIO1_IO05__ GPIO1_...

Page 133: ...level sensitive It is de bounced on the Module Pulled up on Module Driven by OD part on Carrier P129 SER0_TX D7 ALT0 UART4_TXD__ UART4_DCE_TX O Asynchronous serial port data out P130 SER0_RX C6 ALT0...

Page 134: ...LT5 ECSPI2_MOSI__ GPIO5_IO11 Request to Send handshake line for SER2 P139 SER2_CTS C5 ALT5 ECSPI2_SCLK__ GPIO5_IO10 Clear to Send handshake line for SER2 P140 SER3_TX A7 ALT0 UART1_TXD__ UART1_DCE_TX...

Page 135: ...MX8M CPU Type Description Pin Pin Name Ball Mode Signal Name P147 VDD_IN P Power in P148 VDD_IN P Power in P149 VDD_IN P Power in P150 VDD_IN P Power in P151 VDD_IN P Power in P152 VDD_IN P Power in...

Page 136: ...CMSRCGPCMIX _CLKO1 O Master clock output for CSI camera support S7 CSI0_TX I2C_CAM0_DAT F7 ALT0 I2C2_SDA__ I2C2_SDA IO OD Camera0 I2C bus data S8 CSI0_CK B22 ALT0 MIPI_CSI1_CLK_ P I CSI0 differential...

Page 137: ...E1_MDI0 Not used S19 GbE1_LINK100 Not used S20 GbE1_MDI1 Not used S21 GbE1_MDI1 Not used S22 GbE1_LINK1000 Not used S23 GbE1_MDI2 Not used S24 GbE1_MDI2 Not used S25 GND P Ground S26 GbE1_MDI3 Not use...

Page 138: ...SAI2_MCLK O Master clock output to Audio codecs S39 I2S0_LRCK H4 ALT0 SAI2_TXFS__ SAI2_TX_SYNC IO Left Right audio synchronization clock S40 I2S0_SDOUT G5 ALT0 SAI2_TXD0__ SAI2_TX_DATA0 O Digital aud...

Page 139: ...ight audio synchronization clock S51 HDA_SDO I2S2_SDOUT C3 ALT0 SAI3_TXD__ SAI3_TX_DATA0 O Digital audio Output S52 HDA_SDI I2S2_SDIN F3 ALT0 SAI3_RXD__ SAI3_RX_DATA0 I Digital audio Input S53 HAD_CK...

Page 140: ...X_P AI USB3 data receive signal differential pairs positive S66 USB3_SSRX B13 USB1_TX_N AI USB3 data receive signal differential pairs negative S67 GND P Ground S68 USB3 Not used S69 USB3 Not used S70...

Page 141: ...C_RX Not used S80 GND P Ground S81 PCIE_C_TX Not used S82 PCIE_C_TX Not used S83 GND P Ground S84 PCIE_B_REFCK F25 PCIE2_REF_PAD _CLK_P O Differential PCI Express Reference Clock Signals for Lanes A S...

Page 142: ...CIE_B_TX E24 PCIE2_TXN_N O Differential PCIe Link A transmit data pair 0 S92 GND P Ground S93 DP0_LAN0 Not used S94 DP0_LAN0 Not used S95 DP0_AUX_SEL Not used S96 DP0_LANE1 Not used S97 DP0_LANE1 Not...

Page 143: ...eDP1_TX0 DSI1_D0 AIO LVDS1 LCD data channel differential pairs 1 S112 LVDS1_0 eDP1_TX0 DSI1_D0 AIO LVDS1 LCD data channel differential pairs 1 S113 eDP1_HPD Not used S114 LVDS1_1 eDP1_TX1 DSI1_D1 AIO...

Page 144: ...ferential pairs 4 S122 LCD1_BKLT_ PWM Not used S123 RSVD Not used S124 GND P Ground S125 LVDS0_0 eDP0_TX0 DSI0_D0 AIO LVDS0 LCD data channel differential pairs 1 S126 LVDS0_0 eDP0_TX0 DSI0_D0 AIO LVDS...

Page 145: ...DP0_TX2 DSI0_D2 AIO LVDS0 LCD data channel differential pairs 3 S133 LCD_VDD_EN K1 ALT5 SAI1_RXC__ GOIO4_IO1 O High enables panel VDD S134 LVDS0_CK eDP0_AUX DSI0_CLK O LVDS0 LCD differential clock pai...

Page 146: ...0 I2C_LCD_DAT F7 ALT0 I2C2_SDA__ I2C2_SDA IO OD LCD display I2C bus clock S141 LCD_BKLT_PWM E6 ALT1 SPDIF_EXT_CLK__ PWM1_OUT O Display backlight PWM control S142 RSVD Not used S143 GND P Ground S144 e...

Page 147: ...dication to Module Low indicates lid closure which system may use to initiate a sleep state Carrier to float the line in in active state Active low level sensitive Should be de bounced on the Module P...

Page 148: ...be enabled while this signal is held low by the Carrier Pulled up on Module Driven by OD part on Carrier S151 CHARGING T7 ALT0 GPIO1_IO01__ GPIO1_IO1 I Held low by Carrier if DC input for battery char...

Page 149: ...its should not be powered up until the Module asserts the CARRIER_PWR_ON signal S155 FORCE_RECOV I Pulled up on Module Driven by OD part on Carrier S156 BATLOW N7 ALT0 GPIO1_IO08__ GPIO1_IO8 I Battery...

Page 150: ...trol Signals between SMARC Module and Carrier This Chapter points out the handshaking rule between SMARC module and carrier Section include SMARC iMX8M Module Power Power Signals Power Flow and Contro...

Page 151: ...ollow these rules or it might not boot up Some pull up and pull down also need to be cared to make all functions work 4 1 SMARC iMX8M Module Power 4 1 1 Input Voltage Main Power Rail The allowable Mod...

Page 152: ...f used on Carrier shall be protected against charging by a Carrier Schottky diode The diode is placed in series with the positive battery terminal The diode anode is on the battery side and the cathod...

Page 153: ...gnal of the carrier board The module will not boot up till the module power is ready because the carrier board hasn t released the reset signal yet The sequence is as follows Module Power Ready CARRIE...

Page 154: ...ystem is not battery powered only 2 SMARC Module power domain 3 Carrier Circuits power domain The Battery Charger domain includes circuits that are active whenever either charger input power and or ba...

Page 155: ...to 5 25V I2C_PM CARRIER_PWR_ON MODULE CARRIER INTERFACE FET Isolation Carrier Power Supplies should not Come up before assertion of CARRIER_PWR_ON Additional power enables may be implemented by the s...

Page 156: ...154 P155 P156 VDD_IN I PWR 3 0V 5 25V1 Main power supply input for the module P2 S3 P9 S10 P12 S13 P15 S16 P18 S25 P32 S34 P38 S47 P47 P50 P53 P59 S61 S64 S67 P68 S70 S73 P79 S80 P82 S83 P85 S86 P88 S...

Page 157: ...dge Finger I O Type Power Rail Description Pin Pin Name S150 VIN_PWR_BAD I CMOS VDD_IN Power bad indication from Carrier board S154 CARRIER_PWR_O N O CMOS VDD_IO Signal to inform Carrier board circuit...

Page 158: ...OW I CMOS VDD_IO Battery low indication to Module Carrier to float the line in in active state Pulled up on Module Driven by OD part on Carrier S154 CARRIER_PWR_ON O CMOS VDD_IO Signal to inform Carri...

Page 159: ...ep indicator from Carrier board May be sourced from user Sleep button or Carrier logic Carrier to float the line in in active state Active low level sensitive Should be de bounced on the Module Pulled...

Page 160: ...pgrade restore or at factory default where the firmware in eMMC flash is empty or at development stage that the firmware in eMMC needs to be modified users will need an alternative way to boot up from...

Page 161: ...nc 161 SMARC iMX8M Computer on Module User s Manual v 1 0 4 3 Power Flow and Control Signals Block Diagram Following figures shows the power flow and control signals block diagram Figure 27 Power Bloc...

Page 162: ...on the carrier The main body of carrier board circuits will not be powered until the module asserts the CARRIER_PWR_ON signal being correct Module hardware will assert CARRIER_PWR_ON when all power su...

Page 163: ...the CPU and peripherals are not running Only the PMIC is running Carrier board provides power for module the peripheral supplies are not available SUS Suspend System is suspended and waits for wakeup...

Page 164: ...s the carrier board to switch of the power rails for the peripherals The module can be brought back to the running mode in two ways The module main voltage rail VDD_IN can be removed and applied again...

Page 165: ...ule will continue to assert signal RESET_OUT after the release of CARRIER_PWR_ON for a period sufficient time at least 10ms to allow carrier power circuits that the peripheral supplies need to ramp up...

Page 166: ...is allows the operating system to take care of any housekeeping e g bringing mass storage devices to a controlled halt Some operating system may not provide the shutdown function As it is not permitte...

Page 167: ...Embedian Inc 167 SMARC iMX8M Computer on Module User s Manual v 1 0 Figure 30 Shutdown Sequence...

Page 168: ...output RESET_OUT are asserted as long as RESET_IN is asserted If the reset input RESET_IN is de asserted the internal reset and the RESET_OUT will remain low for at least 1ms until they are also de as...

Page 169: ...MI_CTRL_DAT 1 5k pull up to 1 8V Carrier pull up required HDMI_CTRL_CK 1 5k pull up to 1 8V Carrier pull up required PCIE_ A B _TX 0 2uF Capacitor PCIE_ A B _TX 0 2uF Capacitor I2C_PM_DAT 2 2K pull up...

Page 170: ...rmination Notes USB 0 3 _EN_OC 10K pull up to 3 3V or a switched 3 3V on the Module x is 0 or 1 Switched 3 3V if a USB channel is not used then the USBx_EN_OC pull up rail may be held at GND to preven...

Page 171: ...econdary side center tap terminations appropriate for Gigabit Ethernet implementations GBE_LINK GBE status LED sinks If used current limiting resistors and diodes to pulled to a positive supply rail T...

Page 172: ...s required on the Carrier The pull ups may be part of an integrated HDMI ESD protection and control line level shift device such as the Texas Instruments TPD12S016 If discrete Carrier pull ups are use...

Page 173: ...1_AUX_SEL Carrier DP1_AUX_SEL should be connected to pin 13 of the DisplayPort connector to enable a dual mode DisplayPort interface DP1_LANE 0 3 DP1_LANE 0 3 DC blocking capacitors shall be placed on...

Page 174: ...e BOOT_SELx pins are weakly pulled up on the Module and the pin states decoded by module logic The Carrier shall either leave the Module pin Not Connected Float in the table below or shall pull the pi...

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